Abstract: Systems and methods for multi-frame and frame streaming in a Controller Area Network (CAN) with Flexible Data-Rate (FD). In some embodiments, a method may include creating, by a device coupled to a CAN network configured to support a CAN Flexible Data-Rate (FD) protocol, a data frame comprising a field that indicates a multi-frame or streaming transmission, and transmitting the data frame in the multi-frame or streaming transmission. A CAN node may include message processing circuitry configured to receive a data frame comprising a Data Length Code (DLC) field configured to indicate multi-frame operation or streaming operation. The message processing circuitry may be further configured to receive another data frame in the absence of an arbitration process between the data frames.

Abstract: An area-efficient, low voltage ESD protection device (200) is provided for protecting low voltage pins (229, 230) against ESD events by using one or more stacked low voltage NPN bipolar junction transistors, each formed in a p-type material with an N+ collector region (216) and P+ base region (218) formed on opposite sides of an N+ emitter region (217) with separate halo extension regions (220-222) formed around at least the collector and emitter regions to improve the second trigger or breakdown current (It2) and set the snapback voltage (Vsb) and triggering voltage (Vt1) at the desired level.

Abstract: An asymmetric cryptographic integrated circuit 20 and a data processing device 10 in which the integrated circuit 20 is used are disclosed. A security boundary 44 is confined to the interior of integrated circuit 20. A random number generator 50 with a hardware entropy source 54 and an arithmetic unit 62 programmed through microcode 38? to perform a variety of cryptographically useful functions are included within security boundary 44. One of these functions is a primality tester 72. A controller 36 for integrated circuit 20 may cause cryptographically sensitive data, such as large random prime numbers and a clear private key to be generated within the confines of security boundary 44. A symmetric key encryption engine 56 is included within security boundary 44 and used to encrypt the clear private key so that a resulting encrypted private key may be stored outside security boundary 44 in a non-volatile memory 12.

Abstract: A method includes forming a packaged integrated circuit that includes forming a lead frame by separating an outer portion of the metal structure into a plurality of leads by stamping. The plurality of leads have sides with a first concavity. The lead frame is further formed by performing an etch on the sides of the plurality of leads to achieve a second concavity on the sides of leads. The second concavity is greater than the first concavity. A semiconductor die is attached to a center portion of the metal structure. Electrical attachments are made between the die and the leads.

Abstract: Various embodiments of semiconductor manufacturing methods include releasing a transparent carrier from a semiconductor wafer assembly that includes a semiconductor wafer in which a plurality of semiconductor devices are formed, an adhesive layer coupled to the semiconductor wafer, a carrier release layer coupled to the adhesive layer, and the transparent carrier coupled to the carrier release layer. The method further includes controlling a laser system to emit a first beam characterized by first laser parameters toward the adhesive layer, where the first laser parameters are selected so that the first beam will compromise a physical integrity of the adhesive layer. The method further includes, after controlling the laser system to emit the first beam toward the adhesive layer, removing the adhesive layer from the semiconductor wafer.

Abstract: A technique for generating a bit log-likelihood ratio (LLR) in a communication system includes generating a demodulated signal based on a received symbol and a reference symbol. An input for a bit LLR generator is generated based on the demodulated signal and a normalization value that is based on the received symbol or the reference symbol. A bit LLR is generated for the received symbol, using the bit LLR generator, based on the input.

Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes encapsulating a device stack within a molded panel having a frontside and a backside. The device stack contains an upper semiconductor die and an interconnect buffer layer, which is formed over the upper semiconductor die and which is covered by the frontside of the molded panel. Material is removed from the frontside the molded panel to expose the interconnect buffer layer therethrough. One or more frontside redistribution layers are produced over the frontside of the molded panel and electrically coupled to the upper semiconductor die through the interconnect buffer layer. The molded panel is then singulated to yield a microelectronic package including a molded package body containing the device stack.

Abstract: A non-volatile memory (NVM) system has a normal mode, a standby mode and an off mode that uses less power than the standby mode. The NVM system includes an NVM array that includes NVM cells and NVM peripheral circuitry. Each NVM cell includes a control gate. A controller is coupled to the NVM array, applies a voltage to the control gates and power to the peripheral circuitry during the standby mode, and applies an off-mode voltage to the control gates and removes power from the NVM peripheral circuitry during the off mode.

Abstract: An integrated circuit is provided. The integrated circuit may include, but is not limited to, a first node, a second node configured to be coupled to ground, an output driver, and a electrostatic discharge circuit electrically coupled to the first node, the second node, and the output driver. The electrostatic discharge circuit may include, but is not limited a high-pass filter configured to detect an electrostatic discharge event at the first node, a driving stage circuit electrically coupled to the high-pass filter and the output driver, the driving stage circuit configured to receive a signal from the high-pass filter when the high-pass filter detects the electrostatic discharge event and further configured to shunt an input of the output driver to the second node in response to the signal from the high-pass filter, and a step-down circuit electrically coupled to the driving stage circuit and configured to bias the driving stage circuit.

Abstract: Embodiments include systems that include at least one integrated circuit (IC) and methods for their testing. Each IC includes an input interconnect to receive an input signal, a test enable interconnect to receive a test enable signal, and a controller (e.g., a TAP controller) for performing testing of the integrated circuit based on values in at least one register (values corresponding to the input signal). Each IC also includes an input port and a multiplexer coupled to the first input interconnect, the at least one register, and the input port. The multiplexer is controllable to pass the input signal to the input port in response to non-assertion of the test enable signal, and to pass the input signal to the at least one register in response to assertion of the test enable signal. When the system includes multiple controllers, each controller may implement a different opcode-to-instruction mapping.

Abstract: A semiconductor device comprises a plurality of transistor mismatch circuits formed on a semiconductor wafer; and a characterization circuit formed on the semiconductor wafer. The characterization circuit is coupled to receive input provided by the absolute value circuits simultaneously which themselves receive inputs from the mismatch circuits simultaneously and is configured to output a standard deviation of mismatch between transistors in the mismatch circuits.

Abstract: A split gate memory structure includes a pillar of active region having a first source/drain region disposed at a first end of the pillar, a second source/drain region disposed at a second end of the pillar, opposite the first end, and a channel region between the first and second source/drain regions. The pillar has a major surface extending between first and the second ends which exposes the first source/drain region, the channel region, and the second source/drain region. A select gate is adjacent the first source/drain region and a first portion of the channel region, wherein the select gate encircles the major surface the pillar. A charge storage layer is adjacent the second source/drain region and a second portion of the channel region, wherein the charge storage layer encircles the major surface the pillar. A control gate is adjacent the charge storage layer, wherein the control gate encircles the pillar.

Abstract: Temperature dependent biasing for leakage power reduction. In some embodiments, a semiconductor device may include a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device and a logic circuit operably coupled to the biasing circuit, where the voltage is applied to a bulk terminal of one or more transistors within the logic circuit, and where the voltage has a value outside of a voltage supply range of the logic circuit. In another embodiment, a semiconductor device may include a biasing circuit configured to generate a voltage that varies according to a temperature of the semiconductor device and a power switch operably coupled to the biasing circuit, where the voltage is applied to a gate terminal of the power switch, and where the voltage has a value outside of a voltage supply range of the power switch.

Abstract: An SRAM bit cell comprises a first inverter including a PMOS transistor and an NMOS transistor, and a second inverter including a PMOS transistor and an NMOS transistor. The first and second inverters are cross-coupled to each other. A plurality of pass transistors couple the inverters to bit lines. Approximately one-half of a supply voltage is provided to the bit lines during pre-charge operations.

Abstract: Embodiments of methods for forming a semiconductor device that includes a die and a substrate include pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate, and performing a bonding operation to form a die attach layer between the die and the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.

Abstract: Systems and methods for handling wake-up messages in a Controller Area Network (CAN) are described. In some embodiments, a method may include operating a CAN controller in a selected one of a plurality of operating modes in response to the detection of an event or activity on a CAN bus. The method may also include handling, by the CAN controller, a CAN message using a message handling protocol associated with the selected one of the plurality of operating modes, for example, while a host processor operates in a low power mode. In various implementations, each of the plurality of operating modes may correspond to a different amount of power consumption by the CAN controller. The method may further include transmitting a selected one of a plurality of response messages by the CAN controller over the CAN bus, in some cases, without waking up the processor from the low power mode.

Abstract: Systems and methods are provided for monitoring operation of MEMS gyroscopes (110). A test signal generator (124) is configured to generate and apply a test signal to the rate feedback loop (112) of a MEMS gyroscope (110). A test signal detector (126) is coupled to the quadrature feedback loop (114) of the MEMS gyroscope (110) and is configured to receive a quadrature output signal from the quadrature feedback loop (114). The test signal detector (126) demodulates the quadrature output signal to detect effects of the test signal. Finally, the test signal detector (126) is configured to generate a monitor output indicative of the operation of the sensing device based at least in part on the detected effects of the test signal in the quadrature output signal. Thus, the system is able to provide for the continuous monitoring of the operation of the MEMS gyroscope (110).

Abstract: A method of transferring data from a non-volatile memory (NVM) having a plurality of blocks of an emulated electrically erasable (EEE) memory to a random access memory (RAM) of the EEE includes accessing a plurality of records, a record from each block. A determination is made if any of the data signals of the first data signals are valid and thereby considered valid data signals. If there is only one or none that are valid, the valid data, if any is loaded into RAM and the process continues with subsequent simultaneous accesses. If more than one is valid, then the processes is halted until the RAM is loaded with the valid data, then the method continues with subsequent simultaneous accesses of records.

Abstract: A programmable gain amplifier (PGA) includes an op amp, an input circuit, a feedback circuit, and a calibration circuit. The input circuit is connected between a PGA input node and an op-amp input node and selectively applies the analog input signal to the op-amp input node. The feedback circuit is connected between an op-amp output node and the op-amp input node and applies the amplified analog output signal as a feedback signal to the op-amp input node. The calibration circuit is connected between a calibration reference node and the op-amp input node and selectively connects the calibration reference node directly to the op-amp input node without traversing any of the input circuit. The PGA may be implemented as a single-ended or differential amplifier. The PGA avoids reduced linearity resulting from series combinations of switches in the input circuit when configured for its normal operating mode.

Abstract: A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a first layer of a material that can be used as a gate or a dummy gate. An opening is formed in the first layer in the NVM region. The opening is filled with a charge storage layer and a control gate. A select gate, which may be formed from the first layer or from a metal layer, is formed adjacent to the control gate. If it is a metal from a metal layer, the first layer is used to form a dummy gate. A metal logic gate is formed in the logic region by replacing a dummy gate.