Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure (100) includes a trench gate structure (114), a lateral gate structure (118), a body region (124) having a first conductivity type, a drain region (125) and first and second source regions (128, 130) having a second conductivity type. The first and second source regions (128, 130) are formed within the body region (124). The drain region (125) is adjacent to the body region (124) and the first source region (128) is adjacent to the trench gate structure (114), wherein a first portion of the body region (124) disposed between the first source region (128) and the drain region (125) is adjacent to the trench gate structure (114). A second portion of the body region (124) is disposed between the second source region (130) and the drain region (125), and the lateral gate structure (118) is disposed overlying the second portion of the body region (124).

Abstract: Methods and systems are disclosed for frequency-domain frame synchronization for multi-carrier communication systems. Received signals are sampled and converted into frequency domain components associated with subcarriers within the multi-carrier communication signals. A sliding-window correlation (e.g., two-dimensional sliding window) is applied to the received symbols represented in the frequency domain to detect frame boundaries for multi-carrier signals. The sliding-window frame synchronization can be applied by itself or can be applied in combination with one or more additional frame synchronization stages. The disclosed embodiments are particularly useful for frame synchronization of multi-carrier signals in PLC (power line communication) systems.

Abstract: An interface for processing a variable reluctance sensor signal provided by a variable reluctance sensor including an integrator, an arming comparator and a detect circuit. The integrator includes an input for receiving the variable reluctance sensor signal and an output providing an integrated signal indicative of total flux change of the variable reluctance sensor. The arming comparator compares the integrated signal with a predetermined arming threshold and provides an armed signal indicative thereof. The detect circuit provides a reset signal after the armed signal is provided to reset the integrator. A corresponding method of processing the variable reluctance sensor signal is also described.

Abstract: An electronic panel assembly (EPA) includes one or more electronic devices with primary faces having electrical contacts, opposed rear faces and edges therebetween. The devices are mounted primary faces down in openings in a warp control sheet (WCS). Cured plastic encapsulation is formed at least between lateral edges of the devices and WCS openings. Undesirable panel warping during encapsulation is mitigated by choosing the WCS coefficient of thermal expansion (CTE) to be less than the encapsulation CTE. Thin film insulators and conductors couple electrical contacts on various devices to each other and to external terminals, thereby forming an integrated multi-device EPA.

Abstract: A method of making a split gate non-volatile memory (NVM) using a substrate includes etching a recess into an isolation region of an NVM region of the substrate and depositing a conductive layer and a capping layer. A select gate and a control gate are formed in the NVM region, and a dummy gate is formed in a logic region of the substrate. A portion of the capping layer is removed and a salicide block bi-layer is deposited and patterned to form a first opening that exposes a contact portion of the conductive layer over the recess. A silicided region is formed on the contact portion. The substrate is planarized to expose the dummy gate, which is replaced with a metal gate. A second opening is etched through a first interlayer dielectric deposited over the substrate to the silicided region. Contact metal is deposited into the second opening.

Abstract: A method includes: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; and when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, executing the instruction.

Abstract: The power switching apparatus includes an output arranged to provide a sense current depending on a load current, a power switching device, a sense device, and a difference amplification device. The difference amplification device includes a first and a second amplifier input, at least one amplifier output connected to a current sense feedback loop arranged to reduce a difference of potentials between the first and the second amplifier input. A terminal of the power switching device and a terminal of the sense device are connected to an input and another terminal of the power switching device and a second terminal of the sense device are coupled to a first cross-coupling switching module.

Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, an intrinsic base, and a collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: Apparatus are provided for voltage-controlled oscillators and related systems. An exemplary voltage-controlled oscillator includes an active-circuit arrangement that facilitates generation of an oscillating signal, and a resonator arrangement capacitively coupled to the active-circuit arrangement to influence an oscillation frequency of the oscillating signal based on a difference between a first control voltage and a second control voltage.

Abstract: An embodiment of a voltage regulator includes a pass device, a feedback circuit, and an operational amplifier (opamp). A first current conducting terminal of the opamp is coupled to an input voltage node, and a second current conducting terminal of the opamp is coupled to a regulated voltage node. The feedback circuit is coupled between the regulated voltage node and the feedback node, and the feedback circuit is a floating voltage reference configured to produce a feedback signal. The opamp has an input coupled to a feedback node, and an output coupled to a control terminal of the pass device. The opamp provides a signal to the control terminal based on the feedback signal from the feedback node. The control signal causes a current through the pass device to vary to maintain a voltage at the regulated voltage node at a target regulated voltage.

Abstract: A microelectromechanical systems (MEMS) device (58) includes a structural layer (78) having a top surface (86). The top surface (86) includes surface regions (92, 94) that are generally parallel to one another but are offset relative to one another such that a stress concentration location (90) is formed between them. Laterally propagating shallow surface cracks (44) have a tendency to form in the structural layer (78), especially near the joints (102) between the surface regions (92, 94). A method (50) entails fabricating (52) the MEMS device (58) and forming (54) trenches (56) in the top surface (86) of the structural layer (78) of the MEMS device (58). The trenches (56) act as a crack inhibition feature to largely prevent the formation of deep cracks in structural layer (78) which might otherwise result in MEMS device failure.

Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the control electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

Abstract: A method of validating timing issues in a gate-level simulation (GLS) of an integrated circuit design including multiple cells includes running a simulation routine of a behavioral model of the design and obtaining a first simulation result. If there is a possible timing violation at a cell corresponding to a forcing indeterminate value, the simulated output of the cell is forced to a first value and a second simulation result obtained. If this result is negative, a report of apparent timing violations at the cell is generated. If the second simulation result is positive, the output of the cell is then forced to a second value and a third simulation result is obtained. If this result is negative, a report of apparent timing violations at the cell is generated but, if it is positive, a report of no apparent timing violation is generated.

Abstract: A system and method for frequency-selective demodulation is presented. An input signal is received that is modulated by frequency shift keying (FSK) and encodes data at a first and second frequency. The input signal is supplied to a plurality of estimators that include a first estimator configured to detect a first signal at the first frequency, a second estimator configured to detect a second signal at the second frequency, a third estimator configured to detect a third signal at a third frequency, and a fourth estimator configured to detect a fourth signal at a fourth frequency. An output is generated indicating receipt of the data encoded at the first frequency or the second frequency based upon outputs of the first estimator, the second estimator, the third estimator, and the fourth estimator.

Abstract: A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.

Abstract: A protection unit of a subroutine stack accessible by a CPU controlled by one main software program, for storing and removing stack frame(s), the stack protection unit being coupleable to the stack and the CPU, comprising: a processor coupled to a first and a second address register; wherein, when a first stack frame is stored onto the stack and the execution of the main software program is suspended by the CPU due to the execution of a subroutine; the processing unit is adapted to set one access rule based on the first and second address registers, preventing: the ongoing subroutine, from accessing a hardware-protected region of the stack, comprising at least one stack frame associated with a return address from which the main software program resumes execution after termination of the execution of the subroutine. A processor, a method and a computer program are also claimed.

Abstract: A protection unit of an interrupt stack accessible by a CPU controlled by one software program, for storing and removing stack frame(s), the stack protection unit being coupleable to the stack and the CPU, comprising: a processor coupled to a first and a second address register; wherein, when a first stack frame is stored onto the stack and the execution of the software program is suspended by the CPU, responsive to one or more occurring hardware IRQs; the processing unit is adapted to set one access rule based on the first and second address registers, preventing: the occurring ISR to be serviced, from accessing a hardware-protected region of the stack, comprising at least the first stack frame and at least one stack frame associated with one or more suspended IRQs. A processor, a method and a computer program are also claimed.

Abstract: A circuitry for and a method of generating a frequency modulated radar transmitter signal are provided. The circuitry comprises a modulation signal generator for generating a modulation signal having a waveform describing a required frequency modulation of the frequency modulated radar transmitter signal and comprises a PLL circuitry for generating the frequency modulated radar transmitter signal in dependence of the modulation signal. In the PLL circuitry a controllable frequency divider controls the output frequency of the PLL circuitry in dependence of the modulation signal. The PLL circuitry further comprises a phase detector, a controllable oscillator and possibly a low pass filter. The PLL circuitry further comprises a calibration circuitry being configured to control a parameter of at least one of the phase detector and the controllable oscillator to maintain a loop gain of PLL circuitry.

Abstract: A convolutional encoder may have N different states, each having two predecessor states, each branch from each of the two predecessor states having a static code word CW=(B0, B1) and produces a signal having a sequence of the code words. A Viterbi decoding device includes an analog-to-digital conversion unit arranged to extract a soft symbol S=(S1, S2) from the signal; and a digital processing unit connected to the analog-to-digital conversion unit and arranged to compute, for each of the N states, a branch metric value BM_0_K in dependence on the soft symbol S, K being an index identifying the respective state. The digital processing unit may store the soft symbol S as a complex number; and compute a complex branch metric value BM_0_(K, K?)=BM_0_K+J*BM_0_K? in a complex number format on the basis of the soft symbol S, with K different from K?.

Abstract: A method and apparatus for storing trace data within a processing system. The method comprises configuring at least one Error Correction Code, ECC, component within the processing system to operate in a trace data storage operating mode, generating trace data at a debug module of the processing system, and conveying the trace data from the debug module to the at least one ECC component for storing in an area of memory used for ECC information.