Abstract: A plasma display panel has a first substrate, a plurality of address electrodes disposed on the first substrate, a first dielectric layer disposed on the first substrate in covering relation to the address electrodes, a second substrate, a plurality of scan electrodes disposed on the second substrate in a direction transverse to the address electrodes, a second dielectric layer disposed on the second substrate in covering relation to the scan electrodes. The first substrate and the second substrate are disposed in confronting relation to each other with discharge spaces defined therebetween. The first dielectric layer contains electrically conductive particles mixed therewith. The electrically conductive particles make the first dielectric layer electrically conductive in its transverse direction to allow charges stored on the first dielectric layer to leak to the address electrodes for thereby reducing the frequency of random discharges.

Abstract: Disclosed is a magnetic disk apparatus constructed to reduce a track positional deviation of a magnetic head. This magnetic disk apparatus includes a rotary mechanism for rotating the magnetic disk and a rotary type actuator, provided with the magnetic head at its front end, which magnetic head has a write head and a read head, for moving the magnetic head in such a direction as to traverse tracks of the magnetic disk by making rotations about a rotary shaft. A distance A from the center of rotation of the rotary type actuator to the magnetic head is set equal to or larger than a distance B from the center of rotation of the rotary type actuator to the center of rotation of the magnetic disk. Even when separating a write element and a read element, the track positional deviation of the magnetic head can be reduced.

Abstract: A mobile communication system involves a mobile space defined in, for example, a train, and mobile terminals available in the market. When the mobile terminals are used in the mobile space, the system provides them with value-added services exclusive to the mobile space. The system also includes existing base stations each controlling a fixed radio zone that covers a predetermined area, and a mobile base station for controlling a mobile radio zone allocated to the mobile space where the mobile terminals are used. The mobile base station serves as a mobile base station to communicate with the existing base stations, and as a fixed base station to communicate with the mobile terminals when the mobile terminals are in the mobile radio zone. Also provided is a method of controlling such a system.

Abstract: An internal shelled connector, mounted on electric equipment having a grounded chassis panel, for mating with an external cable connector. The connector is encapsulated by a conducting shell for electrostatic shield, except at an opening for receiving the external connector through a corresponding window of the panel. A contact, formed on the shell maintains pressure on a back surface of the panel to ground the shell. The contact may be a flange formed at a tip of a blade spring formed integrally continuous with the conducting shell. The flange maintains a persistent electric contact with the panel, even if the panel and the mounted shelled connector are partially separated due to mechanical stress, when plugging in or pulling out the external cable connector.

Abstract: The invention provides an optical wavelength multiplex transmission method wherein a band in the proximity of a zero dispersion wavelength of an optical fiber is used and optical signals are disposed at efficient channel spacings taking an influence of the band, the wavelength dispersion and the four wave mixing into consideration to realize an optical communication system of an increased capacity which is not influenced by crosstalk by FWM. When optical signals of a plurality of channels having different wavelengths are to be multiplexed and transmitted using an optical fiber, a four wave mixing suppressing guard band of a predetermined bandwidth including the zero-dispersion wavelength &lgr;&thgr; of the optical fiber is set, and signal light waves of the plurality of channels to be multiplexed are arranged on one of the shorter wavelength side and the longer wavelength side outside the guard band.

Abstract: A sector mark detecting circuit for detecting a sector mark on an optical storage medium includes a binarizing circuit which binarizes a reading signal of an optical head in accordance with a predetermined detection parameter and is capable of changing the detection parameter. A recognizing circuit is adapted to recognize a sector mark from an output of the binarizing circuit, and a control circuit is adapted to measure an optimal value of the detection parameter of the binarizing circuit and control the detection parameter of the binarizing circuit to the optimal value. A sector mark detection rate is thereby enhanced.

Abstract: A high electron mobility transistor including an n-type semiconductor layer having a mixed crystal of aluminum gallium arsenide with an aluminum mixed ratio set to fall in the range of 0.2˜0.3, and an undoped semiconductor layer forming a superlattice structure of an electron supplying layer, the undoped semiconductor layer having a mixed crystal of aluminum gallium arsenide with an aluminum mixed ratio set to fall in the proximity of a critical mixed crystal ratio between direct transition and indirect transition.

Abstract: A method of forming a nitride film by a reactive sputtering process includes the steps of (A) sputtering a first nitride film on a substrate by using a target of a refractory metal element under a first sputtering condition set such that a deposition of a nitride of the refractory metal element occurs on the substrate as a result of the sputtering, and (B) sputtering, after the step (A), a second nitride film on the first nitride film by using the target used in the step (A) under a second sputtering condition, wherein the second sputtering condition is set such that no deposition of the nitride occurs on the first nitride film.

Abstract: A restoring circuit 24, provided for each of the memory blocks 191 and 192, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder 26. The present row address is held in one of the registers. When amplification is started by a sense amplifier 15, transfer gates 10 and 11 connected between the bit lines BL1 and *BL1 and the sense amplifier 15 are turned off to decrease the load of the sense amplifier 15, the amplified signal is stored in a buffer memory cell circuit 18, and accessing is completed with omitting restoring to the memory cell 12. While the memory cell block 191 is not selected, the data held in the buffer memory cell circuit 18 is stored into the memory cell row addressed by the content of the selected register. The sense amplifier 15 has PMOS and NMOS sense amplifiers.

Abstract: A lead-free solder alloy composition containing Sn, Ag and Bi, with respective concentrations set such that the lead-free solder alloy has a melting temperature lower than a predetermined heat-resistant temperature of a work to be soldered.

Abstract: A data signal is output from an output circuit of a first chip and sent to a data input terminal in the second chip via a data lead line based on an output clock in first chip, which is sent to the second chip. And an input circuit in a second chip receives the data signal and transfers it inside in response to a transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.

Abstract: A semiconductor device formed on an epitaxial substrate includes a high-resistance region in the vicinity of an interface between a doped semiconductor substrate and an epitaxial layer thereon. The high-resistance region is advantageously formed by an ion implantation process of a dopant opposite to a dopant contained in the doped semiconductor substrate such that there is formed a depletion of carriers in the vicinity of the foregoing interface.

Abstract: One aspect of the present invention is characterized in that an input buffer circuit constitutes either 2 sets, or a plurality of sets relative to 1 input signal, either a pair of complementary internal clocks, or a plurality of internal clocks are generated by frequency-dividing a supplied clock inside the integrated circuit device, and input signals are received and latched either in synchronization with a pair of complementary clocks, or in synchronization with a plurality of clocks in accordance with an input buffer of either 2 sets or a plurality of sets. The output of input buffers of either 2 sets or a plurality of sets are combined by a combining circuit, and supplied internally. An H level or an L level period is set for the internally-generated internal clock so that outputs from the various input buffers are not in contention with one another.

Abstract: A multiaxial optical coupler for use in a device using an LiNbO3 substrate, which is reliable over a wide temperature range and capable of reducing coupling loss. A capillary has a plurality of linear through holes formed therethrough in a manner each inclined with respect to the central axis of the capillary such that the extension line of the central axis of the linear through hole extends through the center of a lens. A plurality of optical fibers are inserted into the linear through holes, respectively. This construction enables the optical axis of an optical beam emitted from each of the optical fibers within the capillary to pass through the center of the lens and reach the end face of a corresponding one of the optical waveguides. Similarly, the construction enables the optical axis of an optical beam emitted from the end face of each of the optical waveguides on the substrate to pass through the center of the lens and reach a corresponding one of the optical fibers within the capillary.

Abstract: An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core.

Abstract: A disk device performs feedforward servo control for moving a head to a target track. The disk device includes a calibrating portion for updating feedforward information, for moving the head, into information dedicated to the specific disk device; and a feedforward information storing portion for storing the feedforward information.

Abstract: A multiplier circuit has an encoder and a partial product bit generating circuit. The encoder receives a multiplier bit signal and is used to output a plurality of encode signals. The partial product bit generating circuit receives the encode signals along with a multiplicand bit signal from each digit place and is used to generate a partial product bit for each digit place. The partial product bit generating circuit has a first selection circuit which is used to select a logically true signal from among the encode signals in accordance with a value of the multiplicand bit signal. Therefore, the circuit can be reduced in size by reducing the number of necessary elements without sacrificing its high speed capability.

Abstract: A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

Abstract: A transfer method of a push-button signal includes the steps of detecting a push-button signal created by an end user terminal during a state in which the end user terminal is connected to a remote service system by an exchange via a network, by using a push-button signal receiver, encoding the push-button signal detected by the push-button signal receiver to a produce a push-button transfer signal by using the push-button signal receiver, and transmitting the push-button transfer signal to the service system from the exchange to the service system via a signal line of the network.

Abstract: An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write operation at one bank of the N banks, a read operation can only be performed on any one of the other N-1 banks. The address buffering and decoding architecture includes a control logic circuit, an address selection circuit located at each of the N banks, and address buffer circuitry. The control logic circuit is used to generate N read select signals to select one bank of the N banks for a read operation and N write select signals to select another bank of the N banks for a write operation. Each address selection circuit is configured to receive from the control logic circuit a respective one of the N read select signals and a respective one of the N write select signals.