Abstract: An interactive terminal system includes a high speed link controller (HSLC) and a number of work stations, all coupled in common to a single conductor coaxial bus. The HSLC includes apparatus controlled by a microprocessor to put the HSLC in a wraparound test mode. The microprocessor transfers test bytes which pass through the HSLC logic and are checked by the microprocessor.

Abstract: A method and apparatus for generating a repetitive serial pattern using a recirculating shift register. Use of a recirculating shift register during a disk formatting operation permits a reduction in the amount of memory contained in a peripheral controller that would otherwise be required to format the disk prior to its being available for normal write and read operations.

Abstract: An auto address development logic that, when provided a starting address, is used to develop consecutive addresses as multiple words of information are presented, one word at a time, during multiple consecutive information transfer cycles. The logic retains for use a current address while simultaneously developing the next address so that the next address will be immediately available as the current address at the beginning of the next information transfer cycle. The auto address development logic is used in a system analyzer connected to a data processing system having a common bus over which the CPU, during a first bus cycle, provides a starting address and requests that the memory fetch multiple words of information which are transferred to the CPU, during multiple subsequent responding bus cycles.

Abstract: A data processing system includes a high speed link controller coupled to a number of work stations by a single coaxial conductor. Apparatus including a counter, a comparator and an adder in the high speed controller synchronizes the data bits received from the work stations to the high speed controller clocking system.

Abstract: A method and apparatus for defining magnetic disk track field lengths using a programmable counter. Use of a programmable counter in a disk controller permits a reduction in the amount of combinational logic that would otherwise be required to be able to perform the various formatting, reading and writing operations involved in use of just one type of disk and makes it possible to perform these operations on a wide variety of disks having different track and sector formats.

Abstract: A memory system includes a plurality of memory controllers which connect to a common bus. Each memory controller includes reconfiguration apparatus which enables the controller when faulty to be switched off line and another controller to be substituted in its place so as to maintain system memory contiguous.

Abstract: A step motor driving circuit, wherein the motor has two pairs of magnetically coupled windings (1, 2 and 3, 4) and includes switching transistors (9, 10, 11, 12) associated to the windings, diodes (15, 16, 17, 18) in parallel to the switching transistors for the recycle of the current induced during the possible current chopping and the phase switching, and a diode (6-8) and a capacitor (5-7), in parallel to each other and series connected between the voltage source, and each pair of magnetically coupled windings. When a phase is de-energized, the driving circuit allows the recovery of the energy stored in such phase by charging the capacitor coupled to it. From such capacitor the energy is then returned to the phase magnetically coupled to the previous one in case of phase switching or to the same phase in case of current chopping. The driving circuit speeds up the phase switching and therefore increases the torque delivered by the motor at high frequencies.

Abstract: Method and apparatus for producing the residue of the product of a multiplier and a multiplicand where the multiplier, multiplicand and product are residues with respect to a check base m, and where m=(2.sup.b -1) and b is the number of bits in a residue. An addressable memory device has at least 2 2(b-1) memory locations with each memory location having an address of 2 (b-1) bits. The address of each memory location can be considered as having two components each of (b-1) bits. The residue stored at each addressable location of the device is the residue of the product of the two components of its address. In response to each address being applied to the memory device, the residue of the product of the two components stored at the addressed memory location is read out of the device. The lower order (b-1) bits of the multiplier is applied to the device if the most significant bit of the multiplier is a logical zero.

Abstract: An annunciator arrangement includes a segmented display unit with segments which may be selectively activated. There is also provided scanning means for scanning a fault line from each of a number of computer components such as voltage regulators to determine the presence or absence of a fault signal thereon. Logic circuitry is provided for selectively displaying on the segmented display units a numerical indication representative of the particular fault line upon which a fault signal has been detected. Such annunciator display is provided at the control panel of the computer rendering it unnecessary for the operator thereof to access the inward parts of the computer in order to determine which component of the computer is indicated as failing.

Abstract: The present invention relates to an alignment network for aligning data words having a plurality of data word formats. A plurality of shifters are utilized, each shifter utilized to shift the corresponding bit of each character. The odd bits, or nonsymmetrical bits across the various data formats are processed by a separate shifter. In this manner, no pre or post processing of the data word is required in the overall shifting operation.

Abstract: Serial printer provided with cutter, the printer being of the type in which printing is performed by a printing head mounted on a carriage sliding on guides parallel to the printing line and a continuous printing support moves perpendicularly to the direction of such guides leaning against a substantially vertical platen. A rotating cutter is lever-mounted on the carriage over the printing head in a position very close to the printing line and it can be actuated in order to partially overlap a cutting edge of the platen, the edge being parallel to the printing line.Owing to the printing head movement along the printing line, the rotating cutter when actuated operates the transversal cutting of the continuous form. The cut form is disposed in a collecting drawer behind the platen owing to the movement imposed by the rotating cutter and to the reduced thickness of the platen which constitutes a drawer wall.

Abstract: The apparatus displays information in a manner which permits viewing at convenient operator locations. It connects to a selected number of points within the computer printed circuit boards of the equipment. The apparatus includes light emitting diode circuits and associated transparent rods for conveying the light indicator information signals to convenient locations for operator viewing. The exposed ends of transparent rod elements are conically shaped so as to concentrate the light indicator signals in sharply defined cones of light so as to be viewed from any angle by an operator located at a considerable distance from the computer equipment.

Abstract: A common bus utilization detection logic that is used when a particular device connected to a common bus has been granted access to the common bus wherein bus access is granted on a priority basis. By positioning the bus utilization logic in priority positions on the common bus adjacent to the particular device whose bus use is to be detected, the bus utilization detection logic can determine when the common bus has been awarded to the particular device even though there may have been other devices simultaneously requesting access to the common bus. The bus utilization detection logic is used in a system analyzer connected to a data processing system having a common bus and permits the analyzer to be connected in the same manner as other devices are connected to the common bus. Also disclosed is a software analyzer and a data processing system having an asynchronous bus on which multiple words of data can be read from memory in response to a read request providing a starting memory address.

Abstract: A hand held tool for installing compression rings includes a pair of relatively reciprocable coaxial cylindrical independently spring biased elements housed within a cylindrical handle which includes mode control means automatically preconditioned for enabling the tool to perform either an installation or ejection operation. The mode control means includes a cylindrical radial cavity containing plural spring biased spherical ball detents and extends into corresponding portion of the outer reciprocable element. The positioning of a tapered central section of the inner reciprocable element coincides with the cavity so that one of the spherical ball detents normally sits within a hollow defined by the taper. When one spherical ball detent, in response to the mode control means being preconditioned by depressing a front end or shaft portion of the inner element, is positioned to lock the outer member to the handle, this allows the ring to be installed onto the cam shaped front end of the outer element.

Abstract: Keyboard coding apparatus couples to a plurality of keys and comprises a scanning interface including a counter (23), a decoder (13) and a multiplexer (22). The scanning interface, in response to each pulse received from a microprocessor (1) through an input lead (11), sends to the microprocessor on an output lead (10) a logic signal indicative of the state of any selected one of the keys. Whenever microprocessor 1 sends a pulse to the scanning interface, it increments by one the contents of an internal register and, before sending another pulse, processes the signal from the scanning interface. When the logic level of such signal indicates a condition of an actuated key, the microprocessor waits a predetermined time interval to establish that said selected key activation is valid, then waits until the selected key has been deactivated and then accesses the character code related to the actuated key from a memory location whose address is latched into its internal register.

Abstract: The present invention relates to a dynamically testable programmable logic array in an unprogrammed state which adds some circuit components to the static test logic. The static test logic provides the capability to detect stuck-at faults at the input of each logic gate of the programmable logic array, and is inoperative during normal operation of the programmable logic array. The added circuit components cause selected inputs to the product array to partially enable the product array, whereby the remaining inputs to the product array are a function of the inputs to the programmable logic array, thereby providing the dynamic test capability.

Abstract: A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which enables the CPU to continually retry the I/O instruction until the IOC accepts or rejects the I/O instruction and which further allows the CPU to suspend the retrying of the I/O instruction and to process interrupt requests and data transfer requests from any one of the plurality of IOCs. After processing the interrupt or data transfer request, system control is returned to retrying the I/O instruction.

Abstract: A minicomputer system is disclosed having a megabus with a plurality of processors and/or subprocessors, input/output (I/O) units and including logic for enabling the detection, decoding, storage and dispatching of data and instructions between the megabus and associated processors. The logic detects information addressed to its associated processors and synchronizes the transfers between the independently timed asynchronous processors and the units attached to the megabus.

Abstract: In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus or for transferring information via a communication channel to other data processing systems during asynchronously generated information bus transfer cycles, an apparatus exists for reformatting data for transfer over the common electrical bus or via the communication channel. The apparatus is comprised of an eight-way multiplexer responsive to control bits for selecting one of eight different formats during write or read operations to or from a memory. Additionally, during read operations, the apparatus transfers a return address from a unit requesting information to the address bus so that data read from memory may be transferred to the requesting device. The formatting control bit is similarly reformatted from the data bus to the address bus bit.

Abstract: In a computer factory data collection terminal an electrical conduit enclosure for permitting wiring to be brought up through the conduit to the factory data collection terminal and for providing full wiring protection while still permitting the terminal to be installed or detached without opening the unit. A conduit enclosure having a base, cover, conduit fittings and special data and address signal connector and power connections is detachably mounted below the data collection terminal.