Abstract: A single computer board data processing system includes a multiport memory system which is accessible by I/O controllers through a system bus I/O memory port or directly by the system's central processing unit (CPU) via a CPU memory port. The logic and control circuits of the memory ports and CPU are included within the computer main board while memory modules/pacs are contained on one or more memory daughter boards which plug into memory input/output connectors contained on the main board. The port address and data paths connect in common to the memory connectors for transmitting and receiving memory addresses and data between the memory modules and the CPU and I/O ports. At least one register connects between the CPU and to common address path.

Abstract: A multilevel set associative cache system whose directory and cache store organized into levels of memory locations. Round robin replacement apparatus is used to identify in which level information is to be replaced. The directory includes error checking apparatus for generating address check bits which are written into directory locations together with addresses. Control apparatus in response to error signals from the error checking apparatus degrades cache operation to those levels detected to be free from errors. Test error mode control apparatus which couples to the replacement and check bit apparatuses causes the address check bits to be selectively forced to incorrect values in response to commands received from a central processing unit enabling the verification of both the checking and control apparatus without interference from other operations initiated by the central processing unit.

Abstract: In an input/output multiplexer of a data processing unit, a plurality of components, capable of independent activity, provide for the simultaneous execution of a multiplicity of operations involving the exchange of signal groups between a central subsystem and peripheral subsystems. The input/output multiplexer includes apparatus for controlling the receipt from delivery to the central subsystem and peripheral subsystems of signal groups. Apparatus is provided to execute address development normally performed in the central subsystem. Apparatus is also provided to analyze control subsystem signal groups and generate pre-selected command signal groups for delivery to the central subsystem or to the peripheral subsystems. Apparatus in the input/output multiplexer also provides a status of each operation currently in execution.

Abstract: In a data processing system, a bus is provided for the transfer of information between units coupled to the bus. The units are coupled in a priority arrangement which is distributed thereby providing priority logic in each of the units and allowing bus transfer cycles to be generated in an asynchronous manner. Priority is normally granted on the basis of physical position on the bus, highest priority being given to the first unit on the bus and lowest priority being given to the last unit on the bus. Each of the units includes priority logic which includes logic elements for requesting a bus cycle, such request being granted if no other higher priority unit has also requested a bus cycle. The request for and an indication of the grant of the bus cycle are stored in each unit so requesting and being granted the bus cycle respectively, only one such unit being capable of having the grant of a bus cycle at any given time, whereas any number of such units may have its request pending at any particular time.

Abstract: A mounting bracket system mounts a factory data collection terminal vertically to a wall to secure the terminal rigidly to the wall surface and also to permit a quick disconnect of the terminal. This is accomplished by fastening two brackets with keyhole slots which are attached to the upper area of the terminal and using two spring loaded captive fasteners which are accessible from the front of the terminal and attached to the bottom of the terminal.

Abstract: In a terminal system comprising a central processor subsystem, a memory subsystem and a plurality of peripheral subsystems, all connected in common to a system bus, the system bus timing is divided into a plurality of fixed times including a central processor (CPU) bus cycle and a plurality of Direct Memory Access (DMA) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles.Particular peripheral subsystems are assigned to particular DMA channels. These DMA channels communicate with the memory subsystem on particular DMA bus cycles which are operative in a revolving priority, with the first DMA bus cycle occuring after the last DMA bus cycle of the previous sequence of DMA bus cycles.A plurality of peripheral subsystems are wired to a particular DMA channel in a daisy chain fashion with the peripheral subsystem wired closest to the system bus having top priority.

Abstract: A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for storing memory requests to be processed. The memory controller further includes control apparatus connected to monitor bus activity. In response to certain bus activity conditions occurring during multiword transfer operations, the control apparatus operates to lengthen the time between successive multiword transfers of data to the bus so as to ensure that new requestors having lower priorities than a memory controller gain access to an available queue notwithstanding the amount of bus delay incurred in transmitting their memory requests.

Abstract: An apparatus for decoding and synchronizing data wherein only logic ZERO data bits are received as electronic pulses, each pulse alternating in opposite directions and wherein logic ONE data bits are received as no pulse. The synchronization logic includes a counter which is delayed a count of binary ONE if the logic ZERO data bit is received late, and the counter is advanced a count of binary ONE if the logic ZERO data bit is received early.

Abstract: A method for achieving printed circuit (PC) board-level testability through electronic component-level design using available technological methods to effect a state of transparency during test, allowing precise verification and diagnosis on a component-by-component basis. Applicable to a greater variety of electronic products than other test methods, and not appreciably constraining functional design, this approach inherently avoids obstacles which prevent other techniques from fulfilling their objectives.

Abstract: An apparatus for varying the pulse width of a computer clock by adding a predetermined amount of time to the clock pulse width. A synchronous counter is combined with a latch into a circuit whereby a pulse input to the circuit resets both the latch and counter on the leading edge, and whereby the trailing edge of the input pulse releases the latch and counter allowing the counter to count clock pulses. On a predetermined pulse the counter's carry-output terminal clocks a logic high into the D latch terminal. Concurrently, an output from the latch is fed back to the counter's count-enable input to disable counting until a subsequent pulse resets the circuit. The net effect is to add a predetermined amount of time to the input pulse so that the extended pulse is available at the output of the latch.

Abstract: A track of a disk device is formatted on a single revolution of the disk by using a read only memory (ROM) to store control codes and a random access memory (RAM) to store address field and data field bytes. A DMA controller simultaneously addresses ROM and RAM. Control codes are read into a control first in-first out memory and data codes are read into a data first in-first out memory. The control codes are applied to a decoder whose output signals control cyclic redundancy check and error detection and correction logic as well as the data first in-first out memory. The serial output from both the data first in-first out memory and the cyclic redundancy check logic are written on disk track.

Abstract: In a data processing system having a plurality of CPUs, each CPU is operatively connected to other portions of the data processing system through a system interface unit. The CPU includes a cache memory, an execution unit, and a control unit. Further, each CPU includes an apparatus for verifying the operability of the CPU independent from the operation of the data processing system, which comprises a switch element, interposed between a first port of the CPU and the system interface unit, for decoupling the CPU from said system interface unit in response to a decoupling control signal. A detecting element, detects whether the CPU and the system interface unit are operatively connected to generate a configuration signal indicating the status of the operative connection. A maintenance panel is connected to the switch element and to the detecting element via a second CPU port.

Abstract: A sense amplifier for a computer memory includes a plural stage differential amplifier. The first stage of the differential amplifier includes an input emitter follower connected to the input of the first stage differential pair. A negative feedback loop is connected around the first stage. The negative feedback loop enhances the response characteristic of the amplifier. Circuit means are also provided which enables the selective steering of energizing current through or away from the second stage of the differential amplifier to provide for the selective blocking of the output of the sense amplifier.

Abstract: A cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of the cache are equal in capacity. The two parts of the cache, designated I-Cache and O-Cache, are semi-independent in their operation and include arrangements for effecting synchronized searches, they can accommodate up to three separate operations substantially simultaneously. Each cache unit has a directory and a data array with the directory and data array being separately addressable. Each cache unit may be subjected to a primary and to one or more secondary concurrent uses with the secondary uses prioritized.

Abstract: A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and an identification section containing circuits for generating signals indicating the board density and the type of memory parts used in constructing the board's memory section. The main board control circuits include a number of decoder circuits which couple to the identification and to the memory section of each memory module board. The decoder circuits receive different address bit combinations of a predetermined multibit address portion of each memory request address.

Abstract: An interactive terminal computer system is disclosed having a system bus for communicating between elements of the computer system which has apparatus for permitting the execution of a maximum number of concurrent bus cycles without interference with each other.

Abstract: An apparatus for encoding data for serial transmission wherein only logic ZEROs are transmitted as electronic pulses, each pulse alternating in opposite direction and wherein logic ONEs require no pulse.

Abstract: Method and apparatus for calculating the residue of a signed binary number of "n" bits with respect to a given check base m where m=2.sup.b -1. The bits of the binary number excluding the sign bit are partitioned into number segments, each of b bits starting with the least significant bit. If (n-1) is not an even multiple of b, higher order bit positions of the number segment containing the next most significant bit of the binary number are filled with logical zeros. A sign segment of b bits is formed. Both number and sign segments have boundaries. The bit position in the sign segment relative to a sign segment boundary which corresponds to the bit position of the sign bit "s" relative to the nearest boundary of a number segment is filled with a logical zero. All other bit positions of the sign segment are filled with the sign bit. The number and sign segments are applied to carry save adders to reduce the number segments and sign segment to a single sum segment and a single rotated carry segment.

Abstract: Method and apparatus for calculating the residue of a binary number of "n" bits with respect to a given check base m where m=2.sup.b -1. The binary number is partitioned into segments, each of b bits starting with the least significant bit. If n is not an even multiple of b, higher order bit positions of the segment containing the most significant bit of the number are filled with logical zeros. The segments are applied to levels of carry save adders to reduce the segments of the binary number to a single sum segment of b bits and a single rotated carry segment of b bits where a rotated carry segment is a carry segment produced by a carry save adder, the most significant bit of which is rotated so that it becomes the least significant bit of the rotated carry segment. Carry segments produced by carry save adders of one level are converted to rotated carry segments before being applied to a carry save adder of a lower level carry save adder.