Abstract: A method and apparatus for addressing a peripheral interface by mapping into the memory address space of a processor contained in a peripheral controller. The processor in the peripheral controller initializes interface logic within the peripheral controller and in the host system peripheral interface logic to which the peripheral controller is attached to either transmit or receive a block of data. Once initialized, units of data are transmitted across the interface between the peripheral controller and host system using a strobe and acknowledge signal to indicate when data can be taken or placed on data lines. The processor is placed in a wait state as each unit of data is transferred and a watch dog timer is provided to detect any transfer that is not completed within the normal response time of the interface.

Abstract: An interactive computer terminal system having a bus for communication between elements of the system is disclosed having apparatus for assigning control of the computer bus on a predetermined order of priority. The CPU receives requests from computer system elements and assigns time slots for use of the system bus by arbitrating among various resources competing for access to the bus.

Abstract: A diskette read data recovery system generates a clock which is locked to an incoming data stream. In a phase locked loop, a signal generated by an oscillator and frequency dividers is compared in phase to the incoming data stream to provide first or second signals depending on whether the incoming data signal leads or lags the clock signal. In order that the system may handle different types of incoming signals, different frequency divider circuits in the phase locked loop are selected for different incoming signals.

Abstract: Apparatus and method for a supervisor for data processing system capable of utilizing a plurality of operating systems. The supervisor includes apparatus for identifying a condition in the data processing system requiring a different operating system. A reserved memory area associated with the currently active operating system is then addressed and register contents of a central processing unit are stored in the reserved memory area. The reserved memory of the operating system being activated is addressed and causes the address of the reserved memory of the operating system being activated, the data related to permitting the physical memory associated with the operating system being activated, contents of registers safestored in the reserve-memory and, data establishing the decor of the operating system being activated are entered in the central processing unit. The operating system to be activated is then enabled, and execution of permitted instructions by the second operating system is begun.

Abstract: Cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of the cache are equal in capacity. The two parts of the cache, designated I-Cache and O-Cache, are semi-independent in their operation and include arrangements for effecting synchronized searches, they can accommodate up to three separate operations substantially simultaneously. Each cache unit has a directory and a data array with the directory and data array being separately addressable. Each cache unit may be subjected to a primary and to one or more secondary concurrent uses with the secondary uses prioritized.

Abstract: A remapping method and apparatus is employed by a memory controller system which includes a microprocessing section which couples to a memory section. The memory section includes a partially good bulk random access memory constructed from a plurality of bit wide chips containing a predefined small number of row or column faults randomly distributed. System columns of chips are organized into a plurality of groups or slices, each of which provide a different predetermined portion of the locations within the partially good bulk memory. A defective-free memory having substantially less capacity is similarly organized. Both memories couple to a static memory which is remapped under the control of the microprocessing section. Prior to remapping, the microprocessing section generates a "slice bit map" indicating the results of testing successive bit groups/slices within the bulk memory locations.

Abstract: In a cache memory unit including a cache directory identifying signal groups stored in an associated cache storage unit, apparatus and method are disclosed for searching the cache directory during a second portion of the cache memory cycle when the cache directory is not needed for normal operation, to determine if an invalid signal group is stored in the associated cache storage. When an invalid signal is found in the cache storage, this signal group is rendered unavailable to the data processing unit during the present cache memory cycle without interrupting the normal cache memory operation during succeeding cache memory cycles.

Abstract: A programmable circuit array comprises an input buffer adapted to receive a plurality of input signals for outputting equivalent input signals and inverted input signals. A programmable product array receives the equivalent input signals and the inverted input signals, for generating a plurality of logical product terms. A programmable sum array combines the plurality of product terms to generate a plurality of sum terms, each of the plurality of sum terms being an output of the programmable circuit array. Test logic is included which selectively causes each of the product terms, the equivalent input signals, and the inverted input signals to have a predetermined logic state in response to at least one control signal.

Abstract: In a data processing system, a stack mechanism creates a stack of operands in a series of memory locations. The memory locations are grouped into stack frames corresponding to the operands included within individual procedures executed by a processing unit of the data processing system. The stack has a maximum number of allocatable storage locations with the actual physical size of the stack being equal to the total number of operands stored therein. The size of the stack is dynamically alterable to conserve usable storage locations in the memory and accessing of operands within a stack frame can be relative to the top or bottom of the stack frame.

Abstract: A memory controller includes a partial defective bulk random access memory having a number of word locations constructed from a plurality of bit wide chips containing a predefined small number of random row or column faults. System columns of chips are organized into a plurality of groups, each group providing a different predetermined portion of the number of word locations. A defect-free memory system having substantially less capacity is similarly organized. Both memories couple to a static memory which stores column addresses associated with good memory locations and slice bit codes specifying the operational status of corresponding bit groups of word locations within both memories. During operation, read/write control circuits read and write valid words from group of bit locations from locations of both memories specified by slice bit codes.

Abstract: A central processor for a general-purpose digital data processing system. The processor has a pair of caches, an operand cache for operands and an instruction cache for instructions, as well as a plurality of execution units, where each execution unit executes a different set of instructions of the instruction repertoire of the central processor. An instruction fetch unit fetches instructions from the instruction cache and stores them in an instruction stack. The central pipeline unit which has five stages obtains instructions of a given program in program order from the instruction stack of the instruction fetch unit.

Abstract: Apparatus and method for providing an improved instruction buffer associated with a cache memory unit. The instruction buffer is utilized to transmit to the control unit of the central processing unit a requested sequence of data groups. In the current invention, the instruction buffer can store two sequences of data groups. The instruction buffer can store the data group sequence for the procedure currently in execution by the data processing unit and can simultaneously store data groups to which transfer, either conditional or unconditional, has been identified in the sequence currently being executed. In addition, the instruction buffer provides signals for use by the central processing unit defining the status of the instruction buffer.

Abstract: An error detection system is disclosed for not only indicating but eliminating certain errors which may occur during the transfer of information between communication busses in a data processing system wherein plural communication busses each provide a common information path to plural data processing units including memory units, peripheral control units, central processing units and ISL units, and wherein each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs. The error detection system requires no special supporting software or firmware on the part of any data processing unit on any of the communication busses.

Abstract: A hardware monitoring interface unit (HMIU) is coupled to a data processing unit and receives all information transferred between subsystems of the data processing unit. Programmable hit matrices (PHM's) include input latches for receiving the information, memory circuits for storing binary ONE's in locations addressed by predetermined portions of the information and output latches for storing the binary ONE's or "hit" signals read from the memory circuits. The "hit" signals are plug-wired into logic circuits and counters in a monitor to collect statistical data.

Abstract: This invention relates to device for detecting a threshold value of the frequency of an input signal. A gate signal is generated from the input signal, whose period has a relationship to the frequency of the input signal. A counter counts pulses from an oscillator having a predetermined rate. The gate signal enables the counter for a predetermined period of time and samples the count at the end of the period of time to determine whether the threshold value has been attained, the count stored in the counter being indicative of the frequency of the input signal.

Abstract: A video generation logic for a display controller includes a precoded PROM which combines visual attributes associated with the characters of information to be displayed on the display screen to produce multiple video control signals for modifying the dot pattern generation signal which is generated in response to character information stored in a refresh memory of the display controller. Visual attribute signals are used as an address to a video attribute generation PROM to retrieve a precoded data word associated with a particular combination of video attributes and the information contained in the retrieved data word is used to provide video control signals. Some of the video control signals are combined with the dot pattern generation signal to provide a video signal which is transmitted to the display monitor which displays the character information.

Abstract: A digital timing unit for timing a data processing system or units thereof, wherein the output signals of a shift register are applied to a plurality of EXCLUSIVE OR gates (G.sub.1) . . . (G.sub.n). The shift register is activated from a known state so that an electric transition signal is shifted through the register cells. A timing cycle is thus defined which is utilized to set the register in a second known state. Feedback and control logic are provided for activating the register independently of its state and keeping it in the state occurring at the end of a timing cycle until a new start signal is received. Shifting of the register is caused by timing pulses generated by an oscillator (1). The timing signals generated by the timing unit and present on the output terminals of the EXCLUSIVE OR may be modified, as to the length, by changing the oscillator period and/or the connection between the EXCLUSIVE OR inputs and the outputs of the shift register.

Abstract: A high speed link controller (HSLC) and a number of work stations are coupled in common to a single conductor coaxial cable. Apparatus generates data signals at high speed for transfer of information between the link controller and the work stations with reduced reflections.

Abstract: A system and method for material control to allow tracking and prevent diversion of articles within the system having a computer connected to a visual display, a keyboard, and printer. The computer is also connected to an OCR device for reading labels associated with articles within the system. Each article is provided with a swerialized initial label when it enters the system having the nature of the article and a serial number disposed thereon. The initial label contains a character field which it is OCR readable by the OCR device. After a reading of the initial label of each article by the OCR device, the computer generates a unique identifying indicia for that article which is utilized by a printer to print a sequential label with the indicia disposed thereon. The sequential label is then associated with the article to allow tracing and to prevent diversion of the article.