Abstract: The present invention discloses a mask set for compensating for a misalignment between the patterns and method of compensating for a misalignment between the patterns. A mask set of the present invention comprises a first mask consisted of a mask substrate on which a main pattern and a plurality of sub-patterns are formed, said sub-patterns formed at a side of the main pattern; a second mask consisted of a mask substrate on which a plurality of hole patterns are formed, the hole patterns corresponded to spaces between the main pattern and the sub-patterns of the first mask, respectively when the first and second mask are overlapped to each other; and a third mask consisted of mask substrate on which a plurality of bar patterns are formed, the bar patterns corresponded to the hole patterns of the second mask, respectively when the second and third mask are overlapped to each other.

Abstract: A ferroelectric memory and method for fabricating the same includes a plurality of first gate electrodes and second gate electrodes formed on an active region of a substrate electrically separated form each other, a plurality of first electrodes of first ferroelectric capacitors each connected to the substrate at one side of the first gate electrode, and a plurality of first electrodes of the second ferroelectric capacitors each connected to the substrate at one side of the second gate electrode. Ferroelectric layers respectively formed on the first electrodes, and second electrodes are formed on the ferroelectric layers. A first metal line electrically couples the plurality of first gate electrodes, and a second metal line electrically couples the plurality of second gate electrodes. The ferroelectric memory has a simplified fabrication process and an increased area of the capacitor that is favorable for high density device packing.

Abstract: The CMOS image sensor includes a pixel array with M(row line)×N(column line) unit pixels, M and N being a positive integer, respectively, wherein each unit pixel includes a light sensing element, coupled to a sensing node, for receiving light from an object to generate photoelectric charges, a resetting unit, coupled to the sensing node, for making a fully depleted region within the light sensing unit and providing a reset voltage level to the sensing node in response to a first control signal, wherein the reset voltage level corresponds to a level of the first control signal and is supplied to a unit pixel of a next row line as a power source, arranged on the same column line, an amplifying unit for amplifying the voltage level of the sensing node to generate an amplified signal, wherein a power source of the amplifying unit is derived from a unit pixel of a previous row line, arranged on the same column line, and a switching unit, coupled between the amplifying unit and an output terminal, for perform

Abstract: An image sensor according to the present invention can detect and correct an error value of a defective pixel. The image sensor includes an error detection circuit for detecting an error by comparing difference between a current pixel value and a previous pixel value with a predetermined reference value and an error correction circuit for correcting an error value from a pixel, by substituting the previous pixel value for the current pixel value.

Abstract: The present invention relates to a pinned photodiode for an image sensor and a method for manufacturing the same; and, more particularly, to a pinned photodiode of an image sensor fabricated by CMOS processes and a manufacturing method thereof The pinned photodiode, according to an embodiment of the present invention, includes a semiconductor layer of a first conductivity type; and at least two first doping regions of a second conductivity type alternately formed in the semiconductor layer and connected to each other at edges thereof so that the first doping regions have the same potential, wherein a plurality of PN junctions is formed in the semiconductor layer and the PN junctions improves a capturing capacity of photoelectric charges generated in the photodiode.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective SiGe epi-silicon growth technology. It relates to manufacturing of a high performance surface channel PMOS salicide that has a number of beneficial effects.

Abstract: A non-volatile memory device includes a floating gate formed over a semiconductor substrate. At one end of the floating gate, there is a tapered protrusion having a horn-like or bird's beak shape. A control gate covers the floating gate except for the tapered protrusion. Sidewall spacers are formed adjacent to the floating gate and the control gate. An erasing gate is formed over the tapered protrusion of the floating gate.

Abstract: An amplifier in a semiconductor integrated circuit includes a current-mirror typed differential amplifier and a cross-coupled differential amplifier, whereby a minute voltage difference from a bit line signal or a data bus signal is amplified. The amplifier for generating an amplified signal includes a load for coupling to a first voltage potential, a first sense amplifier responsive to a first data signal, and a second sense amplifier responsive to a second data signal. The first and second sense amplifiers are commonly coupled to the load, and the amplified signal of the first or second data signal is generated.

Abstract: Disclosed is a channel resource management method in a base station using a dynamic function in a mobile communication system, in which a real-time conversion of a traffic channel to an overhead channel using a dynamic function is allowed when a trouble occurs in the overhead channel of a base station of a mobile communication system adopting code division multiple access(CDMA) system like digital cellular system(DCS) or personal communication system (PCS), and normal servicing of terminal can be maintained by a minimum channel resource conversion resulted from an effective management of channel resource.

Abstract: The present invention provides a method for reducing or eliminating a poor pattern formation on a photoresist film by contacting the photoresist film with an alkaline solution prior to its exposure to light. Methods of the present invention significantly reduce or prevent T-topping and top-loss.

Abstract: A method and apparatus for forward and reverse power control in a mobile telecommunication system, wherein the transfer of power control data between a multi-mode demodulator board assembly and multi-user modulator board assembly installed in a base station is implemented on the basis of an independent power control bus, resulting in the occurrence of no time delay during the power control data transfer. Therefore, a mobile station is reduced in power loss, thereby enhancing the quality of speech.

Abstract: A semiconductor device for use in a memory cell includes an active matrix provided with a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate and conductive plugs electrically connected to the transistors, a number of bottom electrodes formed on top of the conductive plugs, composite films formed on the bottom electrodes and Al2O3 films formed on the composite films. In the device, the composite films are made of (Ta2O5)0.92(TiO2)0.08 by using an atomic layer deposition(ALD).

Abstract: The present invention discloses a method of forming a spin on glass film which can prevent a shift of the threshold voltage of a device by curing the spin on glass film with an electron beam of energy of 6-7 kV.

Abstract: The present invention discloses a Rambus DRAM which can reduce power consumption by restricting generation of an unnecessary clock by improving command decryption when a command is applied with a COLC packet or COLX packet, so that the other packet cannot influence on another device.

Abstract: A semiconductor memory device for performing highspeed address access and highspeed data access is provided by controlling a control/address block in synchronization with a delay locked loop (DLL) clock. The semiconductor memory device includes a clock buffer for buffering an external clock; a delay locked loop (DLL) for generating a DLL clock in synchronization with the external clock; a control signal buffer for receiving and buffering an external control signal to generate an internal control signal in synchronization with the DLL clock; and an address buffer for receiving and buffering an external address signal to generate an internal address signal in synchronization with the DLL clock.

Abstract: A switching device in a digital unit of a multi-sector base station, which uses switching elements incorporated in the digital unit and adapted to switch 3 sectors into multiple sectors, thereby being capable of implementing a multi-sector base station system allowing a softer handoff among all sectors. The switching elements are adapted to support the switching of the next channel element stage in the digital unit included in the existing 3-sector base station to implement a base station system, thereby allowing all handoff between sectors to be conducted in a softer handoff fashion while allowing all channel elements to be set for all sectors covered by the base station upon setting a traffic channel, thereby achieving an efficient allocation of channel elements.

Abstract: A mobile communication system includes a signal processor, a first memory, a controller, and an input-output controller. The signal processor receives first forward GPS data and transmits backward GPS data. The first memory has a preamble area, a base station information area, a time information area, and a location information area and stores the backward GPS data, the first forward GPS data, and second forward GPS data received by an exterior GPS receiver. The controller controls data input and output over the first memory and controls transmission of the backward GPS data stored in the first memory to the signal processor. The input-output controller is controlled by the controller and transmits the second forward GPS data to the first memory.

Abstract: Transistor, is disclosed, including a base having a bundle of (n,n) nanotubes, and an emitter and a collector connected to opposite sides of the base each having (n,m, n−m≠3 l) nanotubes, whereby substantially reducing a device size and improving an operation speed as the carbon nanotube has a thermal conductivity much better than silicon.

Abstract: The stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding-pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame by utilizing a conductive adhesive material. A connecting hole is formed in the outer end of the inner lead for better electrical connection when soldered. The entire resultant structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.

Abstract: A method of forming a via plug in a semiconductor device is disclosed. Metal nuclei are formed on the surface of the metal layer underlying the via hole. The metal layer, which is partially exposed between metal nuclei, is etched by means of a wet etching method, and accordingly, a plurality of etching grooves is formed on the partially exposed surface of the metal layer. As a result, the formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.