Abstract: A method of forming silicide, especially in a CMOS device in which polysilicon grains in a p-type gate are re-doped with n-type impurities such as As and the like at a critical implantation dose. This increases the grain size of the polysilicon, which also reduces sheet resistance by securing thermal stability in subsequent process steps thereof. The present invention generally includes forming an undoped polysilicon layer, doping the polysilicon layer with p-type impurity ions, doping the p-doped polysilicon layer with ions that increase the grain size of the polysilicon layer by being heated, forming a metal layer on the twice-doped polysilicon layer, and forming a silicide layer by reacting a portion of the twice-doped polysilicon layer with the metal layer.

Abstract: A data processing method for a hybrid ARQ type II/III downlink of a wide-band radio communication system, wherein SRNC and CRNC are located on the same radio network, includes the steps of: a) generating RLC-PDU in a RLC layer of the SRNC and generating a PDU having RLC-PDU information needed for supporting the hybrid ARQ type II/III based on a header of the RLC-PDU (HARQ-RLC-Control-PDU); b) transmitting the RLC-PDU and the HARQ-RLC-Control-PDU to a MAC-D, treating a general user part of a MAC layer through a logical channel; c) transmitting the RLC-PDU and the HARQ-RLC-Control-PDU from the MAC-D to a MAC-C/SH, treating common/shared channel part of the MAC layer; d) transforming the PLC-PDU and the HARQ-RLC-Control-PDU to MAC-PDU and the HARQ-MAC-Control-PDU, respectively, in the MAC-C/SH, and allocating a format TFI1 of the MAC-PDU and TFI2 of the HARQ-MAC-Control-PDU, and transmitting the TFI1 and TFI2 to the MAC-D, and transmitting the MAC-PDU and the HARQ-MAC-Control-PDU to a physical layer of BTS, thro

Abstract: The present invention provides a CMOS (Complementary Metal Oxide Semiconductor) image sensor including a unit pixel, wherein the unit pixel includes photodiodes for receiving incident light and for generating photo charges, single sensing node for selectively receiving the photo charges outputted from the photodiodes; a reset transistor for resetting the single sensing node; and a drive transistor for outputting electrical signals corresponding to voltage levels of the single sensing node, and wherein the CMOS image sensor samples the electrical signals through the correlated double sampling and then outputs a final image value to an external device.

Abstract: A semiconductor device for use in a memory cell includes an active matrix provided with a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate and conductive plugs electrically connected to the transistors, a number of bottom electrodes formed on top of the conductive plugs, composite films formed on the bottom electrodes and A2O3 films formed on the composite films. In the device, the composite films are made of (Ta2O5)0.92 (TiO2)0.08 by using an atomic layer deposition (ALD).

Abstract: A method for automatically controlling a semiconductor manufacturing process in a semiconductor factory, includes the steps of: a) receiving a lot specification data and a lot process data; b) comparing the lot specification data with the lot process data to determine whether a difference between the lot specification data and the lot process data is within a predetermined range; c) if a difference between the lot specification data and the lot process data exceeds or falls below a predetermined range, generating a first message representing an occurrence of an abnormally manufactured lot; d) generating a first transaction in response to the first message, the first transaction representing that the lot is abnormally manufactured; and e) storing the first transaction into a storage unit, so that a next lot process to the abnormally manufactured lot is prevented.

Abstract: ESD protection circuit and method for fabricating the same, which has an improved performance, the method including the steps of (1) forming a transistor on a substrate, (2) forming a first insulating film on the substrate inclusive of the transistor and having a first contact hole to an input terminal of the transistor, (3) forming a buffered layer in the first contact hole and the first insulating film in the vicinity of the first contact hole, (4) forming a second insulating film on the first insulating film inclusive of the buffered layer and having a second contact hole to the buffered layer, and (5) forming a pad both on the second contact hole and the second insulating film in the vicinity of the second contact hole.

Abstract: A multistage interrupt controller provides a multistage storage means that processes external interrupt signals, including a plurality of multistage interrupt reception registers that can receive and provide temporary storage for corresponding external interrupt signals, an interrupt priority determining circuit that can receive the external interrupt signals from the multistage interrupt reception registers, determine priorities of the external interrupt signals, and dispose of the external interrupt signals according to the priorities, and a logical operator that inverts signals generated by the corresponding multistage interrupt reception registers and provides a logical feedback signal to the multistage interrupt reception registers.

Abstract: The present invention relates to a pinned photodiode used in a CMOS image sensor. The pinned photodiode according to the present invention has an uneven surface for increasing an area of a PN junction of the photodiode. So, the increased PN junction area improves a light sensitivity of the photodiode. That is, the epitaxial layer, in which the photodiode is formed, has a trench or a protrusion. Also, in the pinned photodiode, since the P0 diffusion layer is directly in contact with the P-epi layer, the two P-type layers have the same potential and then it may operate in a low voltage.

Abstract: A method for manufacturing an aluminum oxide film for use in a semiconductor device, the method including the steps of preparing a semiconductor substrate and setting the semiconductor substrate in a reaction chamber, supplying an aluminum source material and NH3 gas into the reaction chamber simultaneously for being absorbed on the semiconductor substrate, discharging unreacted MTMA or by-product by flowing nitrogen gas into the reaction chamber or vacuum purging, supplying an oxygen source material into the reaction chamber for being absorbed on the semiconductor substrate, and discharging unreacted oxygen source or by-product by flowing nitrogen gas into the reaction chamber or vacuum purging.

Abstract: A TFT-LCD driver includes a TFT-LCD panel having a plurality of gate bus lines, a plurality of source bus lines, a plurality of TFT's, and a plurality of liquid crystal cells corresponding to the plurality of TFT's, a gate driver integrated circuit for supplying driving voltages to the gate bus lines to turn the TFT's on and off, a source driver integrated circuit for sequentially supplying analog voltages to the source bus lines so as to input the analog voltages to the plurality of liquid crystal cells through the turned-on TFT's, and a controller for providing control signals to the gate driver integrated circuit and the source driver integrated circuit, wherein the analog voltages supplied from the source driver integrated circuit to the TFT-LCD panel have the same polarity at least twice in sequence, wherein the source driver integrated circuit drives the TFT-LCD panel using one of a dot inversion method and a pixel inversion method.

Abstract: Solid state image sensor suitable for enhancing sensitivity of charge coupled devices (CCDs) using phase shift of light, and method for fabricating the same, the solid state image sensor including a plurality of photodiodes for generating image charges from incident lights, a plurality of charge coupled devices provided between the photodiodes for transmitting the image charges in one direction, a first flat layer formed on an entire surface of the photodiodes and the charge coupled devices, a plurality of color filter layers formed on the first flat layer to be in correspondence to the photodiodes, a plurality of black layers formed on the first flat layer between the color filter layers, a plurality of phase shift layers selectively formed on the color filter layers to be in correspondence to the photodiodes alternately, a second flat layer formed on an entire surface including the phase shift layers, and a plurality of microlenses formed on the second flat layer to be in correspondence to the photodiodes.

Abstract: A semiconductor device for use in a memory cell including an active matrix provided with a silicon substrate, at least one transistor formed on the silicon substrate, a number of bottom electrodes formed over the transistors, a plurality of conductive plugs to electrically connect the bottom electrodes to the transistors, respectively, and an insulating layer formed around the conductive plugs. In the device, by carrying out a carbon treatment to top surface portions of the bottom electrode structure, it is possible to secure enough space to prevent the formation of bridges between the bottom electrodes.

Abstract: A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.

Abstract: A method for allocating a channel at a BTS of an IMT-2000 system by using channel element information received from a call process block of a BSC (Base Station Controller) so as to allocate the channel element to the boards and to configure the allocated channel element information, is disclosed. The BTS includes a multi-user modulator (MUM), a multi-mode demodulator (MMD) and a combiner & channel decoder (CCD) boards. A storage area is generated to configure a linked list representing a relation between channel allocation information and each of the boards. The channel element allocation message is stored at the storage area and channel information is extracted from the stored channel element allocation message to analyze a sector ID of the channel element. A normal state of MUM, MMD and CCD boards are searched to allocate a channel at the searched MUM, MMD and CCD boards and rewrite the channel allocation information of the MUM, MMD and CCD boards.

Abstract: Metal layer in a semiconductor device and method for fabricating the same, the semiconductor device having a transistor and a capacitor electrode formed on a region of a semiconductor substrate, the metal layer including a planar protection film on an entire surface of the semiconductor substrate inclusive of the transistor and the capacitor electrode, an absorber layer over the planar protection film inclusive of a region over the transistor, an insulating film on an entire surface, with a width of projection in a relievo form in a region over the absorber layer, a via hole through the planar protection film and the insulating layer, to expose a region of the capacitor electrode, a tungsten plug and a planar stuffed layer in the via hole, a mirror metal layer on the insulating film on both sides of the projection of a relievo form of the insulating film, inclusive of the planar stuffed layer, and an insulating film spacer on the projection of a relievo form of the insulating film and the mirror metal layer i

Abstract: An apparatus for controlling a global positioning system (GPS) reference signal to be provided to a base station modem is disclosed to expand a coverage area of a base station, which comprises a GPS clock reception block for generating a system clock and a pp2s signal based on a reference time from the GPS; a system clock distribution block for distributing the system clock received from the clock reception block; a clock generation block for receiving the pp2s signal and generating a clock signal as base station synchronous signals for the expansion of the coverage area; a base station modem block with a multiplicity of base station modems, for performing data modulation/demodulation in synchronism with a corresponding clock signal; a CPU for generating a control signal; and a controller for allowing the data to be transmitted to a selected one among the base station modems, in response to the control signal.

Abstract: A computer simulation method for a semiconductor device manufacturing process, includes: a first step for forming an initial section of the material with only open cells exposed to the growth or etching among the cells; a second step for inputting information including growth or etching points into each open cell; a third step for computing a movement speed for the growth or etching points; a fourth step for moving the growth or etching points for a time determined according to the movement speed; and a fifth step for forming a new etching section by re-arranging the open cells exposed to the growth or etching, after moving the growth or etching points, the second to fifth steps being repeatedly performed on the re-arranged open cells until the sum of the predetermined time reaches the time (T).

Abstract: NAND type non-volatile ferroelectric memory cell and non-volatile ferroelectric memory of the same, in which numbers of access to a main cell and a reference cell are made the same, to maintain bitline induced voltages by the reference cell and by the main cell constant, for improving operation characteristics, minimizing a layout area, and permits a high density device integration, the memory cell including an N number of transistors connected in series, a bitline having an input terminal of a first transistor and an output terminal of (N)th transistor among the N number of transistors connected thereto, wordlines respectively connected to gates of the transistors except the (N)th transistor, a WEC signal line connected to a gate of the (N)th transistor and adapted to have an enable signal applied thereto only in a write or re-store mode, and ferroelectric capacitors respectively connected both to the wordlines and output terminals of the transistors.

Abstract: The present invention discloses a method for forming a bit line of a semiconductor device which can easily perform a contact process of the semiconductor device, by forming parallel rows of I-shaped active regions, a plug poly and a ladder-type bit line. The spacing between adjacent active regions is maintained at the minimum line width. Two word lines of minimum line width and separated by the minimum line width are formed on the active region. The word lines are perpendicular to the active regions. A plug poly is formed on the active region between the word lines. A bit line contact plug is formed over the plug poly and a device isolation region. A bit line of minimum line width contacts the bit line contact plug and aligned generally parallel to the word lines is formed in a ladder-type configuration. That is, one side the lower portion of the contact plug contacts the plug poly, and the upper portion of the other side of the contact plug contacts the bit line.

Abstract: A semiconductor memory device includes a trench type SRAM(Static Random Access Memory) cell having a higher integration than a stack type SRAM. The SRAM cell memory device is provided with a trench formed in a semiconductor substrate and having four side walls therein, wherein a source and drain region of a drive transistor is formed in two of the four side walls, respectively, a pair of active layers respectively having a source and drain regions of a first load transistor is formed on the substrate adjacent to the side walls, and a gate electrode common to the load transistor is formed on a gate oxide film, whereby the gate electrode of the access transistor is vertically formed toward a direction vertical to the semiconductor substrate instead of being formed on the substrate for thereby decreasing an area to be occupied by transistor.