Abstract: Methods for manufacturing electronic devices and devices produced by those methods are disclosed. One such method includes releasably bonding a first surface of a device substrate to a face of a first carrier substrate using a first bonding agent to produce a first composite substrate, where the face of the first carrier substrate includes a pattern of trenches. The method also includes processing the device substrate to manufacture an electronic device on a second surface of the device substrate. The method further includes releasing the device substrate from the first carrier substrate by a releasing agent.

Abstract: The present disclosure is related to non-volatile memory devices comprising a reversible resistivity-switching layer used for storing data. The resistivity of this layer can be varied between at least two stable resistivity states such that at least one bit can be stored therein. In particular this resistivity-switching layer is a metal oxide or a metal nitride. A resistivity-switching non-volatile memory element includes a resistivity-switching metal-oxide layer sandwiched between a top electrode and a bottom electrode. The resistivity-switching metal-oxide layer has a gradient of oxygen over its thickness. The gradient is formed in a thermal oxidation step. Set and reset voltages can be tuned by using different oxygen gradients.

Abstract: Interdigitated electrode arrays are very promising devices for multi-parameter (bio)sensing, for example the label-free detection of nucleic acid hybridization for diagnostic applications. The current disclosure provides an innovative method for the affordable manufacturing of polymer-based arrays of interdigitated electrodes with ?m-dimensions. The method is based on a combination of an appropriate three-dimensional structure and a single and directional deposition of conductive material. The three-dimensional structure can be realized in a polymer material using a molding step, for which the molds are manufactured by electroplating as a reverse copy of a silicon master structure. In order to ensure sufficient electrical isolation and individual, but convenient, accessibility of the sensors in the array, the interdigitated electrode regions need to be complemented with specific features on the three-dimensional structure. Combined with the use of e.g.

Abstract: A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.

Abstract: Disclosed is a method for generating a pulsed transmission signal. The method includes the steps of generating a plurality of transmission bursts by encoding data with a predetermined spreading code, each of the bursts including a train of pulses defining a burst length of the burst; and sizing the transmission bursts to a peak power level within a predetermined limit, thereby forming the transmission signal. The sizing of the transmission bursts includes the step of modifying the amplitude of the pulses of the burst on the basis of a predetermined relationship between the burst length and the peak/average transmission power level. Also disclosed is a transmitter device implementing the method.

Abstract: The present invention relates to a method for obtaining monocrystalline or single crystal nanowires. Said nanowires are grown in a pattern making use of electro-chemical deposition techniques. Most preferred, the electrolytic bath is based on chlorides and has an acidic pH. Single element as well as combinations of two elements nanowires can be grown. Depending on the element properties the obtained nanowire can have metallic (conductive) or semi-metallic (semi-conductive) properties. The observed nanowire growth presents an unusual behavior compared to the classical nanowire template-assisted growth where a cap is formed as soon as the metal grows out of the pattern. Under given conditions of bath composition and potential (current) settings the nanowires grow out of the pattern up to a few microns without any significant lateral overgrowth.

Abstract: A photonic integrated circuit (410) is described comprising at least one signal processing circuit (110). The signal processing circuit (110) comprises at least one input coupling element (120) for coupling incident light from a predetermined incoupling direction into the photonic integrated circuit (410), and at least one output coupling element (130) for coupling light out of the photonic integrated circuit (410) into an outcoupling direction. The relation between the incoupling direction and the outcoupling direction is different from a relation according to the law of reflection and the incoupling direction and the outcoupling direction are substantially the same. Furthermore, an optical sensor probe (400) comprising such a photonic integrated circuit (410) is disclosed.

Abstract: An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.

Abstract: A method for determining a data format for processing data to be transmitted along a communication path is disclosed. In one aspect, the method includes identifying at run-time an operational configuration based on received information on the conditions for communication on the communication path. The method may also include selecting according to the identified operational configuration, a data format for processing data to be transmitted among a plurality of predetermined data formats.

Abstract: A sensor device is provided for determining the presence and/or amount of at least one component in a fluid. The sensor device comprises at least one sensor unit, the at least one sensor unit comprising at least one elongated nanostructure and a dielectric material surrounding the at least one elongated nanostructure. The dielectric material is such that it is selectively permeable for one of the at least one component and is capable of sensing the component permeated through the dielectric material. The sensor device according to preferred embodiments shows good sensitivity and good mechanical strength. The present invention furthermore provides a method for manufacturing such a sensor device and a method for determining the presence and/or amount of at least one component in a fluid using such a sensor device.

Abstract: A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.

Abstract: The present invention relates to a coupler (100) for coupling radiation to one optical element. The coupler (100) comprises a splitter (110) for splitting a received radiation beam in at least two radiation sub-beams, at least two distinct sub-gratings (120a, 120b) adapted for directing radiation sub-beams such that all radiation is coupled out by the coupler into substantially one direction, and a means for guiding (130a, 130b) each of the radiation sub-beams between the splitter and a sub-grating (120a, 120b).

Abstract: A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions.

Abstract: A method is presented for forming mono-crystalline germanium or silicon germanium in a trench. In an embodiment, the method comprises providing a substrate comprising at least one active region that is adjacent to two insulating regions, forming in the active region a trench having a width of less than 100 nm, and forming in the trench a fill layer at a temperature of less than 450° C. that comprises germanium or silicon germanium and substantially fills the trench. The method further comprises heating the fill layer to a temperature sufficient to substantially melt the fill layer and allowing re-crystallization of the substantially melted fill layer, thereby forming mono-crystalline germanium or silicon germanium in the trench. In an embodiment, the method further comprises forming a mono-crystalline germanium or silicon germanium fin by removing at least a portion of the insulating regions. The mono-crystalline fin may be comprised in a fin field-effect-transistor (finFET).

Abstract: A method and system for evaluating a lithographic pattern obtained using multiple-patterning lithographic processing are presented. In one aspect, the method includes aligning a target design with a lithographic pattern. The target design may comprise a first design and a second design. The method further comprises identifying in the lithographic pattern a stitching region based on a region of overlap between the first design and the second design. The method further comprises determining for the identified stitching region whether a predetermined criterion is fulfilled. In some embodiments, determining whether a predetermined criterion is fulfilled may comprise determining a line or trench minimum width. Alternately or additionally, determining whether a predetermined criterion is fulfilled may comprise determining a stitching metric for the identified stitching region, and evaluating whether or not the stitching metric fulfills the predetermined criterion.

Abstract: The invention relates to a method for determining a set of programming conditions for a given type of charge-trapping non-volatile memory device, comprising the steps of: (a) selecting different sets of programming parameters to be applied to the corresponding number of non-volatile memory devices of said type, (b) programming said number of non-volatile memory devices by means of the sets of programming parameters, (c) determining an actual spatial charge distribution of the charge trapping layer of each of the programmed devices, (d) determining the influence of at least one of the programming parameters on the spatial charge distribution, (e) determining an optimised value for at least one of the programming parameters, (f) entering each optimized value in said sets of programming parameters and repeating steps b) to e) at least once.

Abstract: A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips.

Abstract: Disclosed are systems and methods for cleaning semiconductor substrates, wherein a nucleation structure having nucleation sites is mounted facing a surface of the substrate to be cleaned. The substrate and structure are brought into contact with a cleaning liquid, which is subsequently subjected to acoustic waves of a given frequency. The nucleation template features easier nucleation formation than the surface that needs to be cleaned by, for example, causing the template to have a higher contact angle when in contact with the liquid than the substrate surface to be clean. Therefore, bubbles nucleate on the structure and not on the surface to be cleaned.

Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

Abstract: An analogue signal processor (ASP) application-specific integrated circuit (ASIC) is disclosed. The ACIS can be used for remotely monitoring ECG signals of a subject that has reduced power consumption. In one aspect, the ASIC performs the functions of: ECG signal extraction with high resolution using ECG readout channel, feature extraction using a band-power extraction channel, adaptive sampling the ECG signals using an adaptive sampling analogue-to-digital converter, and impedance monitoring for signal integrity using an impedance monitoring channel. These functions enable the development of wireless ECG monitoring systems that have significantly lower power consumption but are more efficient that predecessor systems. In one embodiment, the ASP ASIC consumes 30 ?W from a 2V supply with compression provided by adaptive sampling providing large reductions in power consumption of a wireless ECG monitoring system of which the ASP ASIC forms a part.