Abstract: The present invention relates generally to integrated circuit (IC) fabrication processes. The present invention relates more particularly to the treatment of surfaces, such as silicon dioxide or silicon oxynitride layers, for the subsequent deposition of a metal, metal oxide, metal nitride and/or metal carbide layer. The present invention further relates to a high-k gate obtainable by a method of the invention.

Abstract: A method for forming a semiconductor device is disclosed. The device includes a control electrode on a semiconductor P-channel layer having at least a gate dielectric layer. The gate dielectric layer has an exponentially decreasing density of defect levels Et in as function of energy from the band edges of the adjacent layer (the semiconductor P-channel layer or optionally the capping layer) toward the center of the bandgap of this layer. The method includes selecting at least one parameter of the P-channel semiconductor device such that the inversion carrier injection into the distribution of defect levels deviates from the energy level at the center of the bandgap of a layer adjacent the gate dielectric layer at the same side of the gate dielectric layer as the P-channel layer, with a value not more than about 49%, such as not more than about 40%, for example not more than about 20%, not more than about 10%, even not more than about 5% of that bandgap in eV. In one aspect, this allows reducing NBTI.

Abstract: One inventive aspect relates to a method for forming integrated circuits and circuits obtained therewith. The method of forming a circuit pattern in a device layer of a semiconductor substrate comprises decomposing the circuit pattern in two constituent orthogonal subpatterns. The method further comprises transferring the pattern of a first subpattern to a hard mask layer overlying the device layer. The method further comprises transferring the pattern of the other subpattern to a photosensitive layer overlying the patterned hard mask layer. The method further comprises patterning the device layer using the patterned hard mask layer and the patterned photosensitive layer as a mask. The method further comprises removing the patterned hard mask layer and the patterned photosensitive layer. Furthermore memory or logic circuits obtained using the above technique are described.

Abstract: A method for providing an oxide layer on a semiconductor substrate is disclosed. In one aspect, the method includes obtaining a semiconductor substrate. The substrate may have a three-dimensional structure, which may comprise at least one hole. The method may also include forming an oxide layer on the substrate, for example, on the three-dimensional structure, by anodizing the substrate in an acidic electrolyte solution.

Abstract: A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing process and a second set are variable, selecting multiple combinations of possible layout and process parameter values which meet predetermined ESD constraints; determining an optimum value for at least one other parameter in view of a predetermined design target apart from the predetermined ESD constraints; determining values for fin width (Wfin), gate length (LG) and number of fins (N) on the basis of the optimum value; and manufacturing said MuGFET ESD protection device using the given manufacturing and process values.

Abstract: The present disclosure provides a tunnel field effect transistor (TFET) device comprising at least following segments: a highly doped drain region, a lowly doped up to undoped channel region being in contact with the drain region, the channel region having a longitudinal direction, a highly doped source region in contact with the channel region, the contact between the source region and the channel region forming a source-channel interface, a gate dielectric and a gate electrode covering along the longitudinal direction at least part of the source and channel regions, the gate electrode being situated onto the gate dielectric, not extending beyond the gate dielectric, wherein the effective gate dielectric thickness tgd,eff of the gate dielectric is smaller at the source-channel interface than above the channel at a distance from the source-channel interface, the increase in effective gate dielectric thickness tgd,eff being obtained by means of at least changing the physical thickness tgd of the gate dielectri

Abstract: The present invention relates to a large time constant steering circuit for slowly changing a voltage on a node between at least two discrete voltage levels. The present invention further relates to a slow steering current DAC comprising said large time constant steering circuit. The present invention further relates to an instrumentation amplifier device comprising a current balancing instrumentation amplifier for amplifying an input signal to an amplified output signal and a DC servo-loop for removing a DC-component from the input signal. The present invention further relates to an EEG acquisition ASIC comprising said instrumentation amplifier device.

Abstract: An electrical device comprises analog conversion circuitry having an input and an output. The electrical device is essentially provided for converting a first input signal within a first frequency range applied to the input to a first output signal within a second frequency range different from the first frequency range at the output. The electrical device further comprises a signal adding means for adding at least a portion of the first output signal as second input signal to the first input signal. The analog conversion circuitry is also capable of converting the second input signal, which is within the second frequency range, back to the first frequency range. Additionally, a characteristic deriving means is provided for deriving at least one characteristic of the electrical device from the frequency converted second input signal, which appears at the output of the analog conversion circuitry.

Abstract: The current invention provides a stepping actuator, achieving large range up to ±35 ?m with low operating voltages of 15V or lower and large output forces of up to ±110 ?N. The actuator has an in-plane-angular deflection conversion which allows achieving step sizes varying from few nanometers to few micrometers with a minor change in the design. According to certain embodiments of the invention, the stepping actuator comprises a geometrical structure with a displacement magnification ratio of between 0.15 and 2 at operating voltages of 15V or lower. The present invention also provides a method for forming such stepping actuators.

Abstract: The present disclosure presents a circuit for converting a pulsed input voltage to a DC output voltage. The circuit comprises input nodes for receiving the pulsed input voltage and output nodes for outputting the DC output voltage. The circuit further comprises a first transistor and a second transistor connected between the input and the output nodes in a synchronous rectifier configuration. The first and second transistors each have a gate connected to a driving circuit configured for alternately charging the gates of the transistors whereby the driving circuit comprises an auxiliary circuit not directly connected to the input nodes and configured for providing a predetermined auxiliary supply voltage to the gates. In an embodiment, the auxiliary circuit comprises a buck DC-DC converter of which an input node is connected to the output nodes and of which an output node is connected to the gates.

Abstract: The present invention relates to an integrated photonic device (100) operatively coupleable with an optical element (300) in a first coupling direction. The integrated photonic device (100) comprises an integrated photonic waveguide (120) and a grating coupler (130) that is adapted for diffracting light from the waveguide (120) into a second coupling direction different from the first coupling direction. The integrated photonics device also comprises a refractive element (110) disposed adjacent the grating coupler (130) and adapted to refract the light emerging from the grating coupler (130) in the second coupling direction into the first coupling direction.

Abstract: A microstructure according to embodiments of the present invention comprises a substrate, and a resonant structure having a resonance frequency and comprising a seismic mass and suspension elements for suspending the seismic mass at two opposite sides onto the substrate. The substrate is adapted for functioning as a tuning actuator adapted for applying stress onto the suspension elements, thus changing the stiffness of the suspension elements. This way, the resonance frequency of the microstructure may be adapted to input vibration frequencies which may vary over time or may initially be unknown. By adapting the resonance frequency of the resonant structure, a suitable power may be generated, even in circumstances of variable input frequencies.

Abstract: A piezoelectric bimorph cantilever is used for determining physical parameters in a gaseous or liquid environment. The sensor works as a driven and damped oscillator. Contrary to common cantilever sensor systems, the piezoelectric film of the bimorph cantilever acts as both a sensor and an actuator. Using at least two resonance mode of the bimorph cantilever, at least two physical parameters can be measured simultaneously in a gas or a liquid. An optimized piezoelectric cantilever and a method to produce the cantilever are also described.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

Abstract: A circuit for end-of-burst detection in a portion of a received bit stream is disclosed. The circuit comprises: a first counter for counting the number of bits in the portion, a second counter for counting the number of bit value transitions in the portion, and a circuit for comparing the counted number of bits in the portion and the counted number of bit value transitions therein with preset values, the circuit for comparing is further arranged for generating a signal indicative of end-of-burst detection based on the result of the comparison.

Abstract: A multi-gate device is disclosed. In one aspect, the device includes a substrate having a first semiconductor layer of a first carrier mobility enhancing parameter, a buried insulating layer, and a second semiconductor layer with a second carrier mobility enhancing parameter. The device also includes a first active region electrically isolated from a second active region in the substrate. The first active region has a first fin grown on the first semiconductor layer and having the first mobility enhancing parameter. The second active region has a second fin grown on the second semiconductor layer and having the second mobility enhancing parameter. The device also includes a dielectric layer over the second semiconductor layer which is located between the first fin and the second fin. The first and second fins protrude through and above the dielectric layer.

Abstract: A device for demodulating a stream of data symbols being part of a multicarrier data stream is disclosed. In one aspect, the device includes a platform capable of running processes in parallel. On the platform a parallel code is mapped for demodulating the data symbols. The parallel code is arranged for determining, from at least one previously processed symbol, information for demodulating a currently processed data symbol of the multicarrier data stream. The device may further includes a parallelization module for parallelizing symbols or groups of symbols of the stream of data symbols code according to a modulo-N symbol splitting of the stream of data symbols, wherein N denotes the number of processes that can run in parallel on the platform. The parallelization module is arranged for applying the parallelized stream to the parallel code.

Abstract: A method and device is disclosed for continuously and simultaneously measuring an impedance signal and a biopotential signal on a biological subject's skin. In one aspect, the method includes attaching input and output electrodes to the biological subject's skin and applying a predetermined alternating current having a first frequency to the output electrodes for creating an alternating voltage signal over the input electrodes. The first frequency is above a predetermined minimum frequency. The method also includes measuring an input signal from the input electrodes which includes a biopotential signal and the alternating voltage signal. The method also includes extracting from the input signal the biopotential signal and the alternating voltage signal, and determining the impedance signal from the alternating voltage signal. The alternating voltage signal is extracted by amplifying and demodulating the input signal using a control signal having a frequency equal to the first frequency.

Abstract: A memory circuit with multi-sized sense amplifier redundancy is disclosed. In one aspect, the circuit includes sense amplifiers connected to differential bit-lines and configured to amplify a voltage difference sensed on the differential bit-lines. The sense amplifiers include a first set of smaller sense amplifiers and a second set of larger sense amplifiers redundantly arranged to the first set to form redundant groups which each contain one smaller sense amplifiers and one larger sense amplifiers. The larger sense amplifiers have a failure rate lower than the smaller sense amplifiers. The circuit also includes calibration circuitry connected to enable and disable nodes of each of the sense amplifiers and configured to select for each redundant group either the smaller sense amplifier of the first set or, if the smaller sense amplifier fails, the larger sense amplifier of the second set.

Abstract: A method and apparatus is disclosed for adaptively sampling an analogue signal to increase the sampling rate in the presence of high frequency content within the signal, for example, QRS complex of an ECG signal. In one aspect, a change in a derivative of the analogue signal is used to control a voltage-controlled oscillator to provide a clock signal for an analogue-to-digital converter. The change in the derivative is compared to an automatically controlled threshold value. The clock signal controls the sampling rate of the analogue-to-digital converter so that the sampling rate is increased from one level, where only P and T waves are present to another higher level when the QRS complex has been detected.