Abstract: An article is provided for immobilizing functional organic biomolecules (e.g. proteins, DNA, and the like) through a covalent bond to a thiolate or disulfide monolayer to a metal surface wherein an extra activation step of the surface layer or an activation step of the functional biomolecules or bioreceptors could be avoided. The monolayer can contain, but is not limited to, two moieties. One has a group that resists nonspecific adsorption and another has a group that directly (without activation) reacts with functional groups on the biomolecules. In addition, poly(ethylene oxide) groups are incorporated in the monolayer surfaces to resist the nonspecific adsorption and to enhance the specific affinity interactions. A sensor device including these monolayers is also provided to perform reproducible, sensitive, specific and stable bioanalysis.

Abstract: The present invention relates to a method for forming metal-silicide catalyst nanoparticles with controllable diameter. The method according to embodiments of the invention leads to the formation of ‘active’ metal-suicide catalyst nanoparticles, with which is meant that they are suitable to be used as a catalyst in carbon nanotube growth. The nano-particles are formed on the surface of a substrate or in case the substrate is a porous substrate within the surface of the inner pores of a substrate. The metal-silicide nanoparticles can be Co-silicide, Ni-silicide or Fe-silicide particles. The present invention relates also to a method to form carbon nanotubes (CNT) on metal-silicide nanoparticles, the metal-silicide containing particles hereby acting as catalyst during the growth process, e.g. during the chemical vapour deposition (CVD) process. Starting from very defined metal-containing nanoparticles as catalysts, the diameter of grown CNT can be well controlled and a homogeneous set of CNT will be obtained.

Abstract: A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.

Abstract: A waveguide coupling probe (10) for sending light into an optical waveguide on a substrate or for receiving light from an optical waveguide on a substrate is provided, the waveguide coupling probe comprising an optical element (11) for guiding the light in a propagation direction, the optical element (11) having a facet (15) where the light enters or exits the optical element (11) and means for coupling the light between the optical element (11) and the waveguide. A waveguide coupling probe (10) according to the present invention is characterized in that the light coupling means are formed on the facet (15) and comprise a diffraction structure (14). In a preferred embodiment the optical element (11) may be an optical fiber and the diffraction structure may be a strong diffraction structure, e.g. a metal grating structure. When bringing the waveguide coupling probe (10) in the vicinity of a waveguide on a substrate, the light that is guided by the waveguide may be diffracted into the optical element (11).

Abstract: The present invention provides a method for in-situ cleaning of walls of a reaction chamber, e.g. reactive ion etching chamber, to remove contamination, e.g. copper comprising contamination from the walls. The method comprises converting the contamination, e.g. copper comprising contamination into a halide compound, e.g. copper halide compound and exposing the halide compound, e.g. copper halide compound to a photon comprising ambient, thereby initiating formation of volatile halide products, e.g. volatile copper halide products. The method furthermore comprises removing the volatile halide products, e.g. volatile copper halide products from the reaction chamber to avoid saturation of the volatile halide products, e.g. volatile copper halide products in the reaction chamber in order to avoid re-deposition of the volatile halide products, e.g. volatile copper halide products to the walls of the reaction chamber.

Abstract: A method for producing on-chip interconnect structures on a substrate is provided, comprising at least the steps of providing a substrate and depositing a ruthenium-comprising layer on top of said substrate, and then performing a pre-treatment of the Ru-comprising layer electrochemically with an HBF4-based electrolyte, and then performing electrochemical deposition of copper onto the pre-treated Ru-comprising layer.

Abstract: The present disclosure relates to a method for calibrating transient behaviour of an electrostatic discharge (ESD) test system. The system includes an ESD pulse generator and probe needles for applying a predetermined pulse on a device under test. The probe needles are connected to the ESD pulse generator via conductors. The test system includes measurement equipment for detecting transient behaviour of the device under test by simultaneously capturing voltage and current waveforms the device as a result of the pulse. The method includes the steps of: (a) applying the ESD test system on a first known system with a first known impedance, (b) applying the ESD test system on a second known system with a known second impedance, and (c) determining calibration data for the transient behaviour the ESD test system on the basis of captured voltage and current waveforms, taking into account said known first and second impedances.

Abstract: A method for generating an ultra-wideband communications signal is described. The method includes generating a piecewise linear ultra-wideband baseband signal comprising at least one pulse, based on an inputted data signal; generating a carrier tone having a carrier frequency suitable for wireless transmission; and upconverting the baseband signal with the carrier tone to the carrier frequency. A method for interpreting a received ultra-wideband communications signal, the signal having a center frequency in the RF domain, is also described. The method includes generating at least one local signal template, synchronized with the received ultra-wideband communications signal and having substantially the same center frequency; correlating the received ultra-wideband communications signal with each of the local signal templates in the analog domain, obtaining at least one ultra-wideband baseband signal; and interpreting the at least one ultra-wideband baseband signal to generate a data signal.

Abstract: The present invention relates to a gas sensing device comprising a nanoparticle layer (1) and a quantum dot layer (3) separated from each other by a gas absorption layer (2) which has a thickness which changes upon absorption of a gas. The nanoparticle layer (1) is provided for generating a surface plasmon resonance within a plasmon resonance frequency range upon illumination with light within a light frequency range; the quantum dot layer (3) has an absorption spectrum overlapping with said plasmon resonance frequency range of said nanoparticle layer (1) and shows photoluminescence in a photoluminescence emission frequency range upon absorption of energy within its absorption spectrum. The present invention further relates to a method for fabricating such a gas sensing device and to a method of using such a gas sensing device.

Abstract: A method for the fabrication of electrical interconnects in a substrate is disclosed. In one aspect, the method includes providing a substrate having a first main surface. The method may further include producing a ring structure in the substrate from the first main surface, which surrounds an inner pillar structure and has a bottom surface. The method may further include filling the ring structure with a dielectric material. The method may further include providing a conductive inner pillar structure, thereby forming an interconnect structure, which forms an electrical path from the bottom surface up until the first main surface. This conductive inner pillar structure can for example be provided by removing the inner pillar structure leaving a pillar vacancy and partially filling the vacancy with a conductive material. The dielectric material may be applied in liquid phase.

Abstract: A system for execution of a decoding method is disclosed. The system is capable of executing at least two data decoding methods which are different in underlying coding principle, wherein at least one of the data decoding methods requires data shuffling operations on the data. In one aspect, the system includes at least one application specific processor having an instruction set having arithmetic operators excluding multiplication, division and power. The processor is selected for execution of approximations of each of the at least two data decoding methods. The system also includes at least a first memory unit, e.g. background memory, for storing data. The system also includes a transfer unit for transferring data from the first memory unit towards the at least one programmable processor. The transfer unit includes a data shuffler. The system may also include a controller for controlling the data shuffler independent from the processor.

Abstract: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.

Abstract: A semiconductor device is disclosed. The device comprises a first MOSFET transistor. The transistor comprises a substrate, a first high-k dielectric layer upon the substrate, a first dielectric capping layer upon the first high-k dielectric, and a first gate electrode made of a semiconductor material of a first doping level and a first conductivity type upon the first dielectric capping layer. The first dielectric capping layer comprises Scandium.

Abstract: The invention relates to methods for preparing as-deposited, low-stress and low resistivity polycrystalline silicon-germanium layers and semiconductor devices utilizing the silicon-germanium layers. These layers can be used in Micro Electro-Mechanical Systems (MEMS) devices or micro-machined structures.

Abstract: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.

Abstract: A method is disclosed for analyzing a performance metric of an array type electronic circuit under process variability effects. The electronic circuit has an array with a plurality of array elements and an access path being a model of the array type electronic circuit. The model includes building blocks having all hardware to access one array element in the array. Each building block has at least one basic element. In one aspect, the method includes deriving statistics of the access path due to variations in the building blocks under process variability of the basic elements, and deriving statistics of the full array type electronic circuit by combining the results of the statistics of the access path under awareness of the array architecture.

Abstract: Manufacturing a semiconductor device involves forming (200) a sacrificial layer where a micro cavity is to be located, forming (210) a metal layer of thickness greater than 1 micron over the sacrificial layer, forming (220) a porous layer from the metal layer, the porous layer having pores of length greater than ten times their breadth, and having a breadth in the range 10 nm-500 nanometers. The pores can be created by anodising, electrodeposition or dealloying. Then the sacrificial layer can be removed (230) through the porous layer, to form the micro cavity, and pores can be sealed (240). Encapsulating MEMS devices with a porous layer can reduce costs by avoiding using photolithography for shaping the access holes since the sacrificial layer is removed through the porous membrane.

Abstract: A method of determining a value of a depth of a semiconductor junction of a substrate using a photomodulated optical reflectance measurement technique is disclosed. In one aspect, the method includes obtaining a substrate which has at least a first region including the semiconductor junction. The method further includes obtaining a reference region. the method further includes performing at least one sequence of: a) selecting a set of measurement parameters for the photomodulated optical reflectance measurement, b) measuring on the at least a first region a first optical signal representative of the substrate with the semiconductor junction using the selected set of parameters, c) measuring on the reference region a second optical signal using the selected set of parameters, and d) determining the ratio of the first optical signal to the second optical signal, and thereafter extracting from the ratio the depth of the semiconductor junction.

Abstract: Methods and systems are described for improving optical lithographic processing of a substrate by selecting appropriate system parameters in order to obtain a good image or print of the pattern to be obtained in a resist layer, which includes selecting a set of system parameters for an optical lithographic system having selectable system parameters, thus characterising the optical lithographic system and obtaining transferred lens pupil information. The latter is performed by obtaining, for each point of a set of points within a lens pupil of the optical lithographic system with the selected set of system parameters, a value of at least one optical parameter at a level of the substrate, the at least one optical parameter being a property of a light ray projected towards the substrate from the point of the set of points within the lens pupil. The lens pupil information then is combined with information about the mask to be used for generating the pattern in the resist layer.

Abstract: One inventive aspect relates to a method of selective epitaxial growth of source/drain (S/D) areas. The method includes providing a substrate having a first and a second substrate area, the first area including at least one gate stack. The method includes applying a poly-Si or poly-SiGe top layer on the substrate, the top layer being etchable with the same etch chemistry as the substrate. The method includes removing the poly-Si or poly-SiGe top layer from the first area selectively towards the poly-Si or poly-SiGe top layer in the second area. The method includes removing simultaneously the poly-Si or poly-SiGe top layer on the second area and at least a part of the substrate in the S/D areas of the first area selectively to the gate stack. The method includes performing a selective epitaxial growth of S/D areas in the first area.