Abstract: A method and device for determining, in a non-destructive way, at least the active carrier profile from an unknown semiconductor substrate are disclosed. In one aspect, the method comprises generating 2 m independent measurement values from the m reflected signals and correlating these 2 m measurement values with 2 m independent carrier profile values. The method further comprises generating additional 2 m measurement values to allow determining the active carrier profile and a second parameter profile by correlating the 4 m measurement values with the 4 m profile values. The method further comprises generating a total of 2 m[n.k] measurement values to allow determining [n.k] independent material parameter depth profiles, each material parameter profile having m points.

Abstract: A method for determining the presence of a sacrificial layer under a structure. The method includes providing at least one structure arranged above a substrate having a major surface lying in a plane, the at least one structure being clamped at at least one side. The method further includes exerting a force, such as a mechanical force, on the at least one structure. The force may have a predetermined amplitude and a component perpendicular to the substrate. Still further, the method includes determining the deflection of the at least one structure perpendicular to the plane of the substrate, and correlating the deflection of the at least one structure to the presence of a sacrificial layer between the substrate and the structure.

Abstract: The present invention relates to a device and corresponding method for ultrafast controlling of the magnetization of a magnetic element. A device (100) includes a surface acoustic wave generating means (102), a transport layer (104), which is typically functionally and partially structurally comprised in said SAW generating means (102), and at least one ferromagnetic element (106). A surface acoustic wave is generated and propagates in a transport layer (104) which typically consists of a piezo-electric material. Thus, strain is induced in the transport layer (104) and in the ferromagnetic element (106) in contact with this transport layer (104). Due to magneto elastic coupling this generates an effective magnetic field in the ferromagnetic element (106). If the surface acoustic wave has a frequency substantially close to the ferromagnetic resonance (FMR) frequency ?FMR the ferromagnetic element (106) is absorbed well and the magnetization state of the element can be controlled with this FMR frequency.

Abstract: The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one aspect of the invention is a method for manufacturing a junction comprising forming a first semiconductor material comprising a first dopant having a first concentration and thereupon; forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction.

Abstract: The present invention relates to a method for obtaining enlarged Cu grains in small trenches. More specifically it related to a method for creating enlarged copper grains or inducing super secondary grain growth in electrochemically deposited copper in narrow trenches and/or vias to be used in semiconductor devices.

Abstract: The described system relates to a method for forming a layer of a mono-crystalline semiconductor material on a substrate comprising providing a substrate, growing epitaxially a template comprising at least one monolayer of a semiconductor material on the substrate, thereafter depositing an amorphous layer of said semiconductor material on the template, and performing a thermal treatment or a laser anneal, thereby converting substantially all of the amorphous layer of the semiconductor material into a mono-crystalline layer of said semiconductor material. According to an embodiment, the semiconductor material is Ge, and the substrate is a Si substrate. The template is preferably a few monolayers thick.

Abstract: A method for manufacturing a resistive switching memory device comprises providing a substrate comprising an electrical contact, providing on the substrate a dielectric layer comprising a trench exposing the electrical contact, and providing in the trench at least the bottom electrode and the resistive switching element of the resistive memory device. The method may furthermore comprise providing a top electrode at least on or in the trench, in contact with the resistive switching element. The present invention also provides corresponding resistive switching memory devices.

Abstract: Calibration method for calibrating transient behaviour of a TLP test system. The system comprises a TLP generator, probe needles, nominally impedance matched transmission lines and measurement equipment, connected between the transmission lines and the TLP generator, for detecting transient behaviour of a device under test by simultaneously capturing voltage and current waveforms as a result of generated pulses. The calibration method comprises (a) applying the TLP test system on an open and capturing first voltage and current waveforms; (b) applying the TLP test system on a calibration element having a known finite impedance and a known transient response and capturing second voltage and current waveforms; (c) transforming the captured first and second current and voltage waveforms to the frequency domain, and (d) determining calibration data for the transient behaviour of the TLP test system on the basis of the transformed first and second voltage and current waveforms.

Abstract: A junction-photovoltage method and apparatus for contactless determination of an electrical/physical parameter of a semiconductor structure having at least one p-n junction located at a surface is disclosed. In one aspect, the method includes illuminating the surface with the p-n junction with a light beam of a first wavelength to create excess carriers at the surface. The method also includes modulating the light intensity of the light beam at a single predefined frequency. The method also includes determining a first photo-voltage at a first position inside the illuminated area and a second photo-voltage at least a second position outside the illuminated area. The method also includes calculating an electrical/physical parameter of the semiconductor structure based on the first and second photo-voltage.

Abstract: A method for forming at least one quantum dot at at least one predetermined location on a substrate is disclosed. In one aspect, the method comprises providing a layer of semiconductor material on an insulating layer on the substrate. The layer of semiconductor material is patterned so as to provide at least one line of semiconductor material having a width (wL) and having a local width variation at at least one predetermined location where the at least one quantum dot has to be formed. The local width variation has an amplitude (A) of between about 20 nm and 35 nm higher than the width wL of the at least one line. The at least one line is patterned to form at least one quantum dot. A design for a lithographic mask for use with the method and a method for making such a design are also disclosed.

Abstract: A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ball. The first and second elements are bonded by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a first layer of non-conductive material and the second solder ball is laterally embedded in a second layer of non-conductive material, such that the upper part of the first solder ball and upper part of the second solder ball are not covered by the non-conductive material. A third solder volume is applied on one or both of the embedded first or second solder balls, prior to the bonding.

Abstract: A method and apparatus for real-time/on-line performing of multi-view multimedia applications are disclosed. In one aspect, a method of computing a disparity value of a pixel includes computing from two input images a plurality of first costs for a pixel, each cost associated with a region selected from a plurality of regions a first type, the regions covering the pixel and being substantially equal in size and shape. The method also includes computing from the first costs a plurality of second costs each associated with a region selected from a plurality of regions of a second type, the regions of the second type covering the pixel, at least some of the regions of the second type having a substantially different size and/or shape. The method further includes selecting from the second costs the minimal cost and selecting the corresponding disparity value as the disparity value.

Abstract: The disclosed method and device relates to a bidirectional ESD power clamp, comprising a semiconductor structure (BigNFET; BigPFET) having a conductive path connected between first and second nodes and having a triggering node via which the conductive path can be triggered. An ESD transient detection circuit is connected between the first and second nodes and to the triggering node and comprises a first part for detecting an occurrence of a first ESD transient on the first node. The semiconductor structure is provided on an insulator substrate, such that a parasitic conductive path between said first and second nodes via the substrate is avoided. The ESD transient detection circuit further comprises a second part for detecting an occurrence of a second ESD transient on the second node.

Abstract: A method for forming an emitter structure on a substrate and emitter structures resulting therefrom is disclosed. In one aspect, a method includes forming, on the substrate, a first layer comprising semiconductor material. The method also includes texturing a surface of the first layer, thereby forming a first emitter region from the first layer, wherein the first emitter region has a first textured surface. The method also includes forming a second emitter region at the first textured surface, the second emitter region having a second textured surface.

Abstract: The present invention is related to a photovoltaic device, the device comprising a first layer of a first semiconductor material of a first conductivity type, a second layer of a second semiconductor material of the opposite conductivity type of the first layer, and a third layer of a third porous semiconductor material situated between the first layer and the second layer. The present invention also provides a method for producing the photovoltaic device.

Abstract: The present disclosure is related to method for producing a semiconductor device comprising the steps of: providing a semiconductor substrate (1), comprising active components on the surface of said substrate, depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface, etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26), etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24), wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is

Abstract: A water soluble functional polyethylene glycol-grafted polysiloxane polymer comprising a polysiloxane backbone and polyethylene glycol side chains is provided having the general formula: wherein A is selected from the group consisting of hydrogen, methyl, methoxy and functional polyethylene glycol based chains, B is a functional group for binding biologically-sensitive materials, D is a functional group for binding to a substrate, m is from 3 to 5, v is from 0 to 5, w is from 4 to 11, x is from 0 to 35 and z is from 1 to 33. In order to be water soluble, the polysiloxane polymer h the following properties: x+y+z is from 8 to 40, n is from 8 to 30, and y is from 7 to 35.

Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.

Abstract: The present disclosure provides a method for controlled formation of the resistive switching layer in a resistive switching device. The method comprises providing a substrate (2) comprising the bottom electrode (10), providing on the substrate a dielectric layer (4) comprising a recess (7) containing the metal for forming the resistive layer (11), providing on the substrate a dielectric layer (5) comprising an opening (8) exposing the metal of the recess, and forming the resistive layer in the recess and in the opening.

Abstract: A method of determining non-ideality characteristics introduced on a signal by a transceiver is disclosed. The transceiver has an up-conversion transmitter and a down-conversion receiver. In one aspect, the method includes: a) generating a signal comprising at least one known training symbol, b) up-converting this signal with a first frequency to a first signal in the transmitter, c) transferring the first signal from the transmitter to the receiver, d) down-converting with a second frequency this transferred first signal to a second signal in the receiver, the second frequency being different from but linked to the first frequency, e) detecting at least one of the training symbols in the second signal; and f) separating, in the frequency domain, at least one of the components of at least one of the detected training symbols for determining the non-ideality characteristics.