Abstract: A piezoelectric bimorph cantilever is used for determining physical parameters in a gaseous or liquid environment. The sensor works as a driven and damped oscillator. Contrary to common cantilever sensor systems, the piezoelectric film of the bimorph cantilever acts as both a sensor and an actuator. Using at least two resonance mode of the bimorph cantilever, at least two physical parameters can be measured simultaneously in a gas or a liquid. An optimized piezoelectric cantilever and a method to produce the cantilever are also described.
Abstract: A thermoelectric generator (TEG) and a method of fabricating the TEG are described. The TEG is designed so that parasitic thermal resistance of air and height of legs of thermocouples forming a thermopile can be varied and optimized independently. The TEG includes a micromachined thermopile sandwiched in between a hot and a cold plate and at least one spacer in between the thermopile and the hot and/or cold plate. The TEG fabrication includes fabricating the thermopiles, a rim, and the cold plate.
Type:
Grant
Filed:
July 1, 2005
Date of Patent:
May 25, 2010
Assignee:
IMEC
Inventors:
Paolo Fiorini, Vladimir Leonov, Sherif Sedky, Chris Van Hoof, Kris Baert
Abstract: A method for trimming an effective refractive index of optical waveguiding structures made for example in a high refractive index contrast material system. By compaction of cladding material in a compaction area next to patterns or ridges that are formed in the core material for realizing an optical waveguiding structure, the effective index of refraction of the optical waveguiding structure can be trimmed. Thus, the operating wavelength of an optical component comprising such an optical waveguiding structure can be trimmed. An optical waveguide structure thus obtained is also disclosed.
Type:
Grant
Filed:
January 15, 2009
Date of Patent:
May 25, 2010
Assignee:
IMEC
Inventors:
Jonathan Schrauwen, Dries Van Thourhout, Roeland Baets
Abstract: A device and a method are presented for generating an intermitted oscillating signal comprising a plurality of oscillating portions separated from each other in time. The device and method are suited for communication systems, in particular for Ultra-Wide Bandwidth (UWB) applications. The device comprises a variable oscillator for generating the oscillating portions; switching circuitry for switching on/switching off the variable oscillator at the beginning/end of each oscillating portion; and circuitry for setting initial conditions in the variable oscillator to impose a predefined transient and a characterizing frequency upon each start-up.
Abstract: A detection system having a receiver for detecting a material having a magnetic resonance response to illumination by pulses of ultra-wideband (UWB) electromagnetic radiation is disclosed. The receiver comprises a detector for detecting the pulses after they have interacted with the material, and a discriminator arranged to identify in the detected pulses the magnetic resonance response of the material. By scanning an item tagged with a tag having a material having a magnetic resonant response, by illuminating the item with UWB pulses and identifying in detected pulses the magnetic resonance response of the material, items can be located, imaged, or activated. The magnetic resonance response of the tag can cause activation of the tag. The tag can have a magnetic resonance response arranged to provide an identifiable magnetic resonance signature such that different tags can be identified and distinguished by their signatures.
Abstract: Preferred embodiments provide a method for forming at least one catalyst nanoparticle on at least one sidewall of a three-dimensional structure on a main surface of a substrate, the main surface lying in a plane and the sidewall of the three-dimensional structure lying in a plane substantially perpendicular to the plane of the main surface of the substrate. The method comprises obtaining a three-dimensional structure on the main surface, the three-dimensional structure comprising catalyst nanoparticles embedded in a non-catalytic matrix and selectively removing at least part of the non-catalytic matrix at the sidewalls of the three-dimensional structure to thereby expose at least one catalyst nanoparticle.
Type:
Grant
Filed:
June 26, 2008
Date of Patent:
May 18, 2010
Assignee:
IMEC
Inventors:
Aleksandar Radisic, Philippe M. Vereecken
Abstract: An optical device for optically multiplexing or demultiplexing light of different predetermined wavelengths is provided, the optical device comprising at least one first waveguide (11) and at least one second waveguide (12) formed on a substrate (10), wherein the at least one first waveguide and the at least one second waveguide intersect at an intersection, comprising a diffraction grating structure (13) formed at the intersection. There exists a first wavelength or wavelength band travelling within the first waveguide (11) exciting the grating structure and being diffracted an angle corresponding to an outcoupling direction and there exists a second wavelength or wavelength band, different from the first wavelength or wavelength band, travelling within the second waveguide (12) exciting the grating structure and being diffracted at an angle corresponding to the same outcoupling direction.
Type:
Application
Filed:
April 4, 2008
Publication date:
May 13, 2010
Applicants:
IMEC, UNIVERSITEIT GENT, GENEXIS B.V.
Inventors:
Gunther Roelkens, Dries Van Thourhout, Roel Baets, Gerard Nicolaas Van den Hoven
Abstract: A method for manufacturing a dual work function semiconductor device and the device made thereof are disclosed. In one aspect, a method includes providing a gate dielectric layer over a semiconductor substrate. The method further includes forming a metal layer over the gate dielectric layer. The method further includes forming a layer of gate filling material over the metal layer. The method further includes patterning the gate dielectric layer, the metal layer and the gate filling layer to form a first and a second gate stack. The method further includes removing the gate filling material only from the second gate stack thereby exposing the underlying metal layer. The method further includes converting the exposed metal layer into an metal oxide layer. The method further includes reforming the second gate stack with another gate filling material.
Abstract: The current invention presents a method for thinning wafers. The method uses a two-step process, whereby first the carrier wafer (2) is thinned and in a second step the device wafer (1) is thinned. The method is based on imprinting the combined thickness non-uniformities of carrier (2) and glue layer (3) essentially on the carrier (2), with a resulting low TTV of the wafer (100) after thinning.
Abstract: One inventive aspect relates to a method of controlling the gate electrode in a silicidation process. The method comprises applying a sacrificial cap layer on top of each of at least one gate electrode, each of the at least one gate electrode deposited with a given height on a semiconductor substrate. The method further comprises applying an additional layer of oxide on top of the sacrificial layer. The method further comprises covering with a material the semiconductor substrate provided with the at least one gate electrode having the sacrificial cap layer with the additional oxide layer on top. The method further comprises performing a CMP planarization step. The method further comprises removing at least the material and the additional layer of oxide until on top of each of the at least one gate electrode the sacrificial cap layer is exposed.
Abstract: One inventive aspect relates to an attenuated phase shift mask suitable for hyper NA lithographic processing of a device, to a method of making such a mask and to hyper NA lithographic processing using such a mask. The attenuated phase shift mask is made taking into the effect of the numerical aperture of the lithographic system on which the attenuated phase shift mask is to be used.
Abstract: A method of forming a crystalline silicon layer on a microrough face of a substrate by reducing the microroughness of the face and then performing a metal induced crystallization process on the face is disclosed. The method further comprises, after metal induced crystallization and before removing the metal layer, removing silicon islands using the metal layer as a mask.
Abstract: The present invention is related to a photovoltaic device, the device comprising a first layer of a first semiconductor material of a first conductivity type, a second layer of a second semiconductor material of the opposite conductivity type of the first layer, and a third layer of a third porous semiconductor material situated between the first layer and the second layer. The present invention also provides a method for producing the photovoltaic device.
Type:
Grant
Filed:
September 8, 2003
Date of Patent:
April 27, 2010
Assignees:
IMEC, FernUniversitat Hagen
Inventors:
Renat Bilyalov, Alexander Ulyashin, Jef Poortmans, Wolfgang Fahrner
Abstract: A catalyst particle for use in growth of elongated nanostructures, such as e.g. nanowires, is provided. The catalyst particle comprises a catalyst compound for catalyzing growth of an elongated nanostructure comprising a nanostructure material without substantially dissolving in the nanostructure material and at least one dopant element for doping the elongated nanostructure during growth by substantially completely dissolving in the nanostructure material. A method for forming an elongated nanostructure, e.g. nanowire, on a substrate using the catalyst particle is also provided. The method allows controlling dopant concentration in the elongated nanostructures, e.g. nanowires, and allows elongated nanostructures with a low dopant concentration of lower than 1017 atoms/cm3 to be obtained.
Type:
Application
Filed:
December 19, 2007
Publication date:
April 22, 2010
Applicant:
Interuniversitair Microelektronica Centrum (IMEC)
Inventors:
Francesca Iacopi, Philippe M. Vereecken
Abstract: For improved scalability of resistive switching memories, a cross-point resistive switching structure is disclosed wherein the plug itself is used to store the resistive switching material and where the top electrode layer is self-aligned to the plug using, for example, chemical-mechanical-polishing (CMP) or simply mechanical-polishing.
Type:
Application
Filed:
August 31, 2007
Publication date:
April 15, 2010
Applicants:
NXP, B.V., INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
Abstract: In the preferred embodiments, a method to reduce gate leakage and dispersion of group III-nitride field effect devices covered with a thin in-situ SiN layer is provided. This can be obtained by introducing a second passivation layer on top of the in-situ SiN-layer, in combination with cleaning of the in-situ SiN before gate deposition and before deposition of the second passivation layer.
Abstract: A method for improving the mechanical hardness of polymer particles is provided, the method comprising subjecting the polymer particles to a thermal cycle of heating and subsequently cooling. The method is applicable for use with combinations of preferably three monomers, the monomers having hydrophilic and hydrophobic groups in their polymer chain in order to achieve preferential orientation of the polymer chains in a polar solvent after applying the heating cycles of the invention (for example, but not limited to, polymethylmethacrylate and polystyrene based terpolymers and copolymers). Polymeric abrasives used in slurry compositions for polishing copper and their use in a chemical mechanical polishing method are also provided.
Abstract: One inventive aspect relates to a method of lithographic processing of a device). The method may be performed using a lithographic processing system and applying a reticle). Lithographic processing of a device typically is characterized by focus conditions, a set of selectable lithographic processing system parameter values and selectable reticle parameter values. The method of configuring the lithographic processing comprises receiving values for the lithographic processing system parameters and for the reticle parameters. The method further comprises receiving focus conditions for the lithographic processing, the focus conditions allowing separation of image performance effects due to lithographic processing system aberrations and image performance effects due to reticle shadowing effects. The method further comprises determining image performance effects due to lithographic processing system aberrations and the image performance due to reticle shadowing effects.
Abstract: A novel nanostructure device operating in Junction Field Effect Transistor (JFET) mode is provided that avoids the majority of the carriers that interact with the interface (e.g. surface roughness, high-k scattering).
Type:
Application
Filed:
October 6, 2008
Publication date:
April 8, 2010
Applicant:
Interuniversitair Microelektronica Centrum vzw (IMEC)
Abstract: A microcomputer architecture comprises a microprocessor unit and a first memory unit, the microprocessor unit comprising a functional unit and at least one data register, the functional unit and the at least one data register being linked to a data bus internal to the microprocessor unit. The data register is a wide register comprising a plurality of second memory units which are capable to each contain one word. The wide register is adapted so that the second memory units are simultaneously accessible by the first memory unit, and so that at least part of the second memory units are separately accessible by the functional unit.