Abstract: A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region and a second transistor in a second region of a substrate, the first transistor including a first gate stack, the first gate stack having a first gate dielectric capping layer and a first metal gate electrode layer. The second gate stack is similar to the first gate stack. The method includes applying a first thermal budget to the first gate dielectric capping layer and a second thermal budget to the second gate dielectric capping material to tune the workfunction of the first and second gate stack, the first thermal budget being smaller than the second thermal budget such that after the thermal treatment the first and the second gate stack have different work functions.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.

Abstract: Tunable vibration energy scavengers and methods of operating the same are disclosed. The disclosed energy scavengers comprise a beam with a main body, wherein the beam comprises at least one flap and means for changing a shape of the at least one flap, wherein the at least one flap is physically attached to the main body along a longitudinal side of the main body. The disclosed methods comprise tuning the shape of the at least one flap, thereby tuning the stiffness of the structure.

Abstract: Methods and apparatus for adaptive encoding of at least a part of a current frame of a sequence of frames of framed data are described which operate on a block-by-block coding basis. The methods and apparatus divide at least a part of the current frame into blocks and then perform a first sub-encoding step on a block. Thereafter a second sub-encoding step is performed on the first sub-encoded block whereby the second sub-encoding step is optimized by adapting its encoding parameters based on a quantity of the first sub-encoded part of the current frame. The quantity is determined by prediction from a reference frame. Then the same steps are performed on another block of the part of the current frame. Typically, the framed data will be video frames for transmission over a transmission channel. The adaptation of the parameters for the second sub-encoding step may be made dependent upon the characteristics or limitations, e.g. bandwidth limitation, of the channel.

Abstract: A method for removing impurities from at least one semiconductor device layer during manufacturing of a semiconductor device is disclosed. The semiconductor device layer has a compound semiconductor material and/or germanium. Each heating process performed during the manufacturing of the semiconductor device after provision of the semiconductor device layer has a low thermal budget determined by temperatures equal to or lower than about 900° C. and time periods equal to or lower than about 5 minutes. In one aspect, the method includes providing a germanium gettering layer with a higher solubility for the impurities than the semiconductor device layer. The germanium gettering layer is provided at least partly in direct or indirect contact with the at least one semiconductor device layer, such that impurities can diffuse from the at least one semiconductor device layer to the germanium gettering layer.

Abstract: A method for producing one or more nMOSFET devices and one or more pMOSFET devices on the same semiconductor substrate is disclosed. In one aspect, the method relates to the use of a single activation anneal that serves for both Si NMOS and Ge pMOS. By use of a solid phase epitaxial regrowth (SPER) process for the Si nMOS, the thermal budget for the Si NMOS can be lowered to be compatible with Ge pMOS.

Abstract: A method for doping a fin-based semiconductor device is disclosed. In one aspect, the method comprises patterning at least one fin, each fin comprising a top surface and a left sidewall surface and a right sidewall surface. The method further comprises providing a first target surface being the right sidewall of a first block of material. The method further comprises scanning a first primary ion beam impinging on the first target surface with an incident angle ? different from zero degrees and thereby inducing a first secondary ion beam, and doping at least the left sidewall surface and possibly the top surface of the fin opposite to the first target surface with the first secondary ion beam.

Abstract: A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning method.

Abstract: A technique is described for the preparation of polymers according to a process in which the starting compound of formula (I) is polymerized in the presence of a base in an organic solvent. No end chain controlling agents are required during the polymerisation to obtain soluble precursor polymers. The precursor polymer such obtained comprises structural units of the formula (II). In a next step, the precursor polymer (II) is subjected to a conversion reaction towards a soluble or insoluble conjugated polymer by thermal treatment. The arylene or heteroarylene polymer comprises structural units of the formula III. In this process the dithiocarbamate group acts as a leaving group and permits the formation of a precursor polymer of structural formula (II), which has an average molecular weight from 5000 to 1000000 Dalton and is soluble in common organic solvents. The precursor polymer with structural units of formula (II) is thermally converted to the conjugated polymer with structural formula (III).

Abstract: Systems and methods for controlling a micro electromechanical device using power actuation are disclosed. The disclosed micro electromechanical systems comprise at least one electrostatically actuatable micro electromechanical device and an actuation device. The micro electromechanical device comprises a first conductor and a second conductor having a moveable portion which in use may be attracted by the first conductor as a result of a predetermined actuation power. The actuation device comprises a high frequency signal generator for generating at least part of the actuation power by means of a predetermined high frequency signal with a frequency higher than the mechanical resonance frequency of the moveable portion of the micro electromechanical device.

Abstract: A dual workfunction semiconductor device and a device made thereof is disclosed. In one aspect, the device includes a first gate stack in a first region and a second gate stack in a second region. The first gate stack has a first effective workfunction, and the second gate stack has a second effective workfunction different from the first effective workfunction. The first gate stack includes a first gate dielectric capping layer, a gate dielectric host layer, a first metal gate electrode layer, a barrier metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode. The second gate stack includes a gate dielectric host layer, a first metal gate electrode, a second gate dielectric capping layer, and a second metal gate electrode.

Abstract: A system and method for estimating remaining run-time of an autonomous system by indirect measure is disclosed. In one aspect, the system includes a load circuit, an energy storage system (ESS) and an energy storage management system (ESM). The load circuit includes functional blocks. The ESS stores electric energy and is connected to the load circuit and configured to supply the varying electric current to the load circuit. The ESM is configured to estimate a remaining run-time of the autonomous system. The ESM includes an input connected to one of the functional blocks of the load circuit from which a first parameter being an indirect measure for the varying electric current supplied from the energy storage system to the load circuit is received. The ESM determines the remaining run-time from this first parameter.

Abstract: The present invention is related to a slurry composition for polishing copper integrated with tungsten containing barrier layers and its use in a CMP method. The present invention is also related to a method for polishing copper integrated with tungsten containing barrier layers by means of an aqueous solution containing abrasive particles, an inorganic acid such as HNO3 as etchant for copper that prevents galvanic corrosion of the tungsten containing metal barrier and at least one organic compound to provide sufficient copper corrosion inhibition.

Abstract: A method for the selective removal of a high-k layer such as HfO2 over silicon or silicon dioxide is provided. More specifically, a method for etching high-k selectively over silicon and silicon dioxide and a plasma composition for performing the selective etch process is provided. Using a BCl3 plasma with well defined concentrations of nitrogen makes it possible to etch high-k with at a reasonable etch rate while silicon and silicon dioxide have an etch rate of almost zero. The BCl3 comprising plasmas have preferred additions of 10 up to 13% nitrogen. Adding a well defined concentration of nitrogen to the BCl3/N2 plasma gives the unexpected deposition of a Boron-Nitrogen (BxNy) comprising film onto the silicon and silicon dioxide which is not deposited onto the high-k material. Due to the deposition of the Boron-Nitrogen (BxNy) comprising film, the etch rate of silicon and silicon dioxide is dropped down to zero.

Abstract: A wavelength-sensitive detector is provided that is based on elongate nanostructures, e.g. nanowires. The elongate nanostructures are parallel with respect to a common substrate and they are grouped in at least first and second units of a plurality of parallel elongate nanostructures. The elongate nanostructures are positioned in between a first and second electrode, the first and second electrodes lying respectively in a first and second plane substantially perpendicular to the plane of substrate, whereby all elongate nanostructures in a same photoconductor unit are contacted by the same two electrodes. Circuitry is added to read out electrical signals from the photoconductor units. The electronic density of states of the elongate nanostructures in each unit is different, because the material, of which the elongate nanostructures are made, is different or because the diameter of the elongate nanostructures is different.

Abstract: A method is provided for incorporating zeolite crystals in patterned structures, the zeolite crystals having pores (channels) with an orientation which is defined by the topology of the zeolite crystal type and the geometry of the patterned structure, resulting in pores parallel with the length axis of the patterned structures. The patterned structures may be vias (vertical contacts) and trenches (horizontal lines) in a semiconductor substrate. These zeolite crystals can advantageously be used for dense and aligned nanocarbon growth or in other words growth of carbon nanostructures such as carbon nanotubes (CNT) within the pores of the zeolite structure. The growth of CNT is achieved within the porous structure of the zeolite crystals whereby the pores can be defined as confined spaces (channels) in nanometer dimensions acting as a micro-reactor for CNT growth.

Abstract: A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises providing a substantially planar layer having a first metal layer, depositing a via level dielectric layer, patterning the via level dielectric layer, at least partly etching the via level dielectric layer, depositing a disposable layer on the at least partly etched via level dielectric layer, patterning the disposable layer, depositing a second metal layer, planarizing second metal layer, depositing permeable dielectric layer after planarizing the second metal layer, and removing the disposable layer through the permeable dielectric layer to form air gaps.

Abstract: The present invention is related to a slurry composition for polishing copper integrated with tungsten containing barrier layers and its use in a CMP method. The present invention is also related to a method for polishing copper integrated with tungsten containing barrier layers by means of an aqueous solution containing abrasive particles, an inorganic acid such as HNO3 as etchant for copper that prevents galvanic corrosion of the tungsten containing metal barrier and at least one organic compound to provide sufficient copper corrosion inhibition.

Abstract: A system and method for converting on a computer environment a first code into a second code to improve performance or lower energy consumption on a targeted programmable platform is disclosed. The codes represent an application. In one aspect, the method includes loading on the computer environment the first code and for at least part of the variables within the code the bit width required to have the precision and overflow behavior as demanded by the application. The method further includes converting the first code into the second code by grouping operations of the same type on the variables for joint execution on a functional unit of the targeted programmable platform, the grouping operations using the required bit width, wherein the functional unit supports one or more bit widths, the grouping operation being selected to use at least partially one of the supported bit widths.

Abstract: The present invention is related to a method and apparatus for cleaning a semiconductor substrate including on a surface of the substrate at least one structure comprising a first conducting or semiconducting material, surrounded by a layer of a second conducting or semiconducting material, said layer essentially extending over the totality of said surface, the first and second material being in physical contact, the method comprising the steps of: providing the substrate, positioning a counter-electrode facing the substrate surface, and supplying an electrolytic fluid to the space between the surface and the electrode, the counter-electrode acting as an anode in the galvanic cell defined by the substrate surface, the cleaning fluid and the counter-electrode.