Abstract: An electronic circuit includes at least one field effect transistor that is to be protected against electrostatic discharge events, and at least one protection field effect transistor. The protection field effect transistor has a crystal orientation that is different from a crystal orientation of the field effect transistor to be protected.
Type:
Grant
Filed:
September 7, 2007
Date of Patent:
March 30, 2010
Assignees:
Infineon Technologies AG, IMEC VZW.
Inventors:
Christian Russ, David Trémouilles, Steven Thijs
Abstract: A method of bonding two elements such as wafers used in microelectronics applications is disclosed. One inventive aspect relates to a method for bonding comprising producing on a first main surface of a first element a first solder ball, producing on a first main surface of a second element a second solder ball, providing contact between the first solder ball and the second solder ball, bonding the first element and the second element by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a nonconductive material, such that the upper part of the first solder ball is not covered by the non-conductive material. Devices related to such methods are also disclosed.
Type:
Grant
Filed:
April 16, 2007
Date of Patent:
March 30, 2010
Assignee:
IMEC
Inventors:
Walter De Raedt, Steven Brebels, Steven Sanders, Tom Torfs, Eric Beyne
Abstract: A method is disclosed for manufacturing SrxTiyO3 based metal-insulator-metal (MIM) capacitors using a low temperature Atomic Layer Deposition (ALD) process. Preferably TiN is used to form the bottom electrode. The Sr/Ti ratio in the SrxTiyO3 dielectric layer of the capacitor can be varied to tune the electric properties of the capacitor. The dielectric constant and the leakage current of the SrxTiyO3 dielectric layer decrease monotonously with the Sr content of this SrxTi1-xO3 dielectric layer. By increasing the Sr content at the interface between the SrxTiyO3 dielectric layer and the TiN bottom electrode, the interfacial equivalent-oxide thickness (EOT) can be further reduced.
Type:
Application
Filed:
September 22, 2009
Publication date:
March 25, 2010
Applicant:
IMEC
Inventors:
Jorge Kittl, Mihaela Ioana Popovici, Nicolas Menou, Dirk Wouters
Abstract: A method for removing a hardened photoresist from a semiconductor substrate. An example method for removing a hardened photoresist layer from a substrate comprising a low-? dielectric material preserving the characteristics of the low-k dielectric material includes: a)—providing a substrate comprising a hardened photoresist layer and a low-? dielectric material at least partially exposed; b)—forming C?C double bonds in the hardened photoresist by exposing the hardened photoresist to UV radiation having a wavelength between 200 nm and 300 nm in vacuum or in an inert atmosphere; c)—breaking the C?C double bonds formed in step b) by reacting the hardened photoresist with ozone (O3) or a mixture of ozone (O3) and oxygen (O2) thereby fragmenting the hardened photoresist; and d)—removing the fragmented photoresist obtained in step c) by wet processing with cleaning chemistries.
Type:
Application
Filed:
September 17, 2009
Publication date:
March 25, 2010
Applicant:
IMEC
Inventors:
Quoc Toan Le, Els Kesters, Guy Vereecke
Abstract: A method is provided for growing mono-crystalline nanostructures onto a substrate. The method comprises at least the steps of first providing a pattern onto a main surface of the substrate wherein said pattern has openings extending to the surface of the substrate, providing a metal into the openings of the pattern on the exposed main surface, at least partly filling the opening with amorphous material, and then annealing the substrate at temperatures between 300° C. and 1000° C. thereby transforming the amorphous material into a mono-crystalline material by metal mediated crystallization to form the mono-crystalline nanostructure.
Abstract: A method is provided for fabricating a porous elastomer, the method comprising the steps of: providing a predetermined amount of a liquid elastomer and a predetermined amount of a porogen; mixing the liquid elastomer and the porogen in vacuum until a homogenous emulsion without phase separation is formed; curing the homogenous emulsion until polymerizations of the emulsion is reached, thereby forming a cured emulsion; and removing the porogen from the cured emulsion. The method can advantageously be used for forming biocompatible porous elastomers and biocompatible porous membranes.
Type:
Application
Filed:
September 21, 2009
Publication date:
March 25, 2010
Applicant:
IMEC
Inventors:
Fabrice Axisa, Pritesh Dagur, Jan Vanfleteren
Abstract: A method and magnetic device for improving the desirable properties of a magnetic device, e.g., magnetization uniformity and reproducibility. Moreover the invention provides magnetic cells that are more magnetically homogeneous, with smaller amount of end domain magnetization canting from the average cell magnetization direction. The invention may provide a magnetic memory cell with less variation in switching fields, more spatially coherent dynamical magnetic properties for high speed and processional or coherent magnetic switching, and higher signal due to the increased uniformity. It may provide a magnetic sensor with more spatially coherent magnetic properties for high speed and processional or coherent magnetic switching, and increased signal. It may provide a read head element with more spatially coherent magnetic properties for high speed and processional or coherent magnetic sensing, and increased signal.
Type:
Grant
Filed:
April 4, 2006
Date of Patent:
March 23, 2010
Assignee:
IMEC
Inventors:
Wayne Hiebert, Jo De Boeck, Liesbet Lagae, Roel Wirix-Speetjens
Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.
Abstract: A method is presented for obtaining characteristics of a target physical entity by providing an excitation signal to the target physical entity and simultaneously measuring the response of the target physical entity. Analog signal processing is performed on the measured response to eliminate artifacts arising from a signal path outside the target physical entity and determining the characteristics from the signal processed measured response. The excitation signal and the analog signal processing are selected such that after analog signal processing of the measured signal, the analog measured signal contains artifacts which are localized in time.
Abstract: The invention relates to an N-bit digital-to-analogue converter (DAC) system, comprising—a DAC unit comprising an N-bit master DAC and a slave DAC, yielding a master DAC unit output signal and a slave DAC unit output signal, respectively, said N-bit master DAC having an output step size,—an adder unit combining the master DAC unit output signal and the slave DAC unit output signal, and—a means for storing correction values for at least the master DAC, said correction values being used by the slave DAC, whereby the DAC system is arranged for master DAC output corrections with a size in absolute value higher than half of the output step size.
Type:
Grant
Filed:
May 2, 2005
Date of Patent:
March 2, 2010
Assignees:
Interuniversitair Microelektronica Centrum (IMEC), Universiteit Hasselt
Abstract: Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 ?mol/cm2 of one or more organometallic compounds containing Al, in a flow of less than 5 ?mol/min. The preferred embodiments are equally related to the semiconductor structure obtained by the method, and to a device comprising said structure.
Abstract: A technique is described for the preparation of polymers according to a process in which the starting compound of formula (I) is polymerized in the presence of a base in an organic solvent. No end chain controlling agents are required during the polymerization to obtain soluble precursor polymers. The precursor polymer such obtained comprises structural units of the formula (II). In a next step, the precursor polymer (II) is subjected to a conversion reaction towards a soluble or insoluble conjugated polymer by thermal treatment. The arylene or heteroarylene polymer comprises structural units of the formula III. In this process the dithiocarbamate group acts as a leaving group and permits the formation of a precursor polymer of structural formula (II), which has an average molecular weight from 5000 to 1000000 Dalton and is soluble in common organic solvents. The precursor polymer with structural units of formula (II) is thermally converted to the conjugated polymer with structural formula (III).
Abstract: A piezoelectric bimorph cantilever is used for determining physical parameters in a gaseous or liquid environment. The sensor works as a driven and damped oscillator. Contrary to common cantilever sensor systems, the piezoelectric film of the bimorph cantilever acts as both a sensor and an actuator. Using at least two resonance mode of the bimorph cantilever, at least two physical parameters can be measured simultaneously in a gas or a liquid. An optimized piezoelectric cantilever and a method to produce the cantilever are also described.
Abstract: A method of forming a crystalline silicon layer on a microrough face of a substrate by reducing the microroughness of the face and then performing a metal induced crystallization process on the face is disclosed.
Type:
Grant
Filed:
June 7, 2005
Date of Patent:
February 16, 2010
Assignee:
IMEC
Inventors:
Dries Els Victor Van Gestel, Guy Beaucarne
Abstract: A method and device for determining the quality of the interface surface between a layer of a dielectric material and the top surface of the semiconductor substrate are disclosed. In one aspect, the method comprises providing a semiconductor substrate with a top surface whereon a layer of a dielectric material is deposited thereby forming an interface surface, the surface of the layer of the dielectric material being or not in direct contact with the semiconductor substrate defining a top surface. A charge is then applied on a dedicated area of the top surface. A voltage Vs is measured on the top surface. The dedicated area is illuminated to define an illuminated spot. The photovoltage is measured inside and outside the determined illuminated spot during the illumination of the area.
Type:
Grant
Filed:
May 28, 2008
Date of Patent:
February 16, 2010
Assignees:
IMEC, Semilab Semiconductor Physics Laboratory, Inc.
Abstract: A method is provided for controlling the average stress and the strain gradient in structural silicon germanium layers as used in micromachined devices. The method comprises depositing a single silicon germanium layer on a substrate and annealing a predetermined part of the deposited silicon germanium layer. The process parameters of the depositing and/or annealing steps are selected such that a predetermined average stress and a predetermined strain gradient are obtained in the predetermined part of the silicon germanium layer. Preferably a plasma assisted deposition technique is used for depositing the silicon germanium layer, and a pulsed excimer laser is used for local annealing, with a limited thermal penetration depth. Structural silicon germanium layers for surface micromachined structures can be formed at temperatures substantially below 400° C., which offers the possibility of post-processing micromachined structures on top of a substrate comprising electronic circuitry such as CMOS circuitry.
Type:
Application
Filed:
December 21, 2006
Publication date:
February 11, 2010
Applicants:
INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC), AMERICAN UNIVERSITY CAIRO
Abstract: The present invention provides a method for dielectric passivating the surface of a solar cell by accumulation of negative fixed charges of a first type at the interface between semiconductor material and a passivating material. According to the invention the passivating material comprises an oxide system, for example a binary oxide system, comprising Al2O3 and at least one metal oxide or metalloid oxide which enhances the tetrahedral structure of Al2O3, for example, an (Al2O3)x(TiO2)1-x alloy. In this way it is possible to combine the desirable properties from at least two different oxides, while eliminating the undesirable properties of each individual material. The oxide system can be deposited onto the semiconductor surface by means of a sol-gel method, comprising the steps of formation of the metal oxide and/or metalloid oxide sol and the aluminum solution and then carefully mixing these together under stirring and ultrasonic treatment.
Type:
Grant
Filed:
June 17, 2004
Date of Patent:
February 9, 2010
Assignee:
IMEC
Inventors:
Guido Agostinelli, Jozef Szlufcik, Petko Vitanov, Antoaneta Harizanova
Abstract: Contact structures and methods for forming such contact structures are disclosed. An example contact structure includes a layer of semiconductor material having an interface and an electrical contact at the interface of the layer of semiconductor material, where the electrical contact includes a granular metal. An example method for forming a contact structure includes providing a substrate and producing a granular metal on at least part of the substrate, where the granular metal includes a cluster of metal islands extending essentially in a two-dimensional plane. The method further includes depositing a layer of a semiconductor material on top of the substrate and the cluster of metal islands.
Abstract: A wireless communication device is provided. The device comprises a digital circuit, an analog circuit, and a control circuit. The digital circuit is arranged to perform digital processing in a signal path. The analog circuit is arranged to perform analog processing in the signal path. The control circuit is arranged to receive control signals as input and arranged to provide output control signals for the analog circuit.
Abstract: The present invention discloses an analogue-to-digital converter comprising at least two voltage comparator devices. Each of the voltage comparator devices comprises a differential structure of transistors and is arranged for being fed with a same input signal and for generating an own internal voltage reference by means of an imbalance in the differential structure, said two internal voltage references being different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of the input signal.
Type:
Grant
Filed:
August 13, 2008
Date of Patent:
January 26, 2010
Assignee:
IMEC
Inventors:
Geert Van der Plas, Johan Bauwelinck, Zhisheng Li, Guy Torfs, Jan Vandewege, Xin Yin