Abstract: A method for manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method relates to providing a substrate with a first and a second region. A gate dielectric is formed overlying the first and the second region. A metal gate layer is formed overlying the gate dielectric on the first and the second region. The metal gate layer has a first (as-deposited) work function that can be modified upon inducing strain thereon. The method further relates to selecting a first strain which induces a first pre-determined work function shift (?WF1) in the first (as-deposited) work function of the metal gate layer on the first region and selectively forming a first strained conductive layer overlying the metal gate layer on the first region, the first strained conductive layer exerting the selected first strain on the metal gate layer.

Abstract: The present invention provides a method for in-situ cleaning of walls of a reaction chamber, e.g. reactive ion etching chamber, to remove contamination, e.g. copper comprising contamination from the walls. The method comprises converting the contamination, e.g. copper comprising contamination into a halide compound, e.g. copper halide compound and exposing the halide compound, e.g. copper halide compound to a photon comprising ambient, thereby initiating formation of volatile halide products, e.g. volatile copper halide products. The method furthermore comprises removing the volatile halide products, e.g. volatile copper halide products from the reaction chamber to avoid saturation of the volatile halide products, e.g. volatile copper halide products in the reaction chamber in order to avoid re-deposition of the volatile halide products, e.g. volatile copper halide products to the walls of the reaction chamber.

Abstract: A digital receiver is disclosed. In one aspect, the receiver includes a receiving module for receiving packetized data. The receive may further include a first processing module for packet detection having a first programmable processor. The receiver may further include a second processing module for demodulation and packet decoding having a second programmable processor. The receiver may further include a first digital receive controller having a third processor arranged for being notified of detection of data by the first processing module and for activating the second processing module.

Abstract: A method according to one embodiment of the invention relates to determining at least one parameter of a model that provides information about a position of an object. The object may include a plurality of alignment marks of which desired positions are known. The method includes measuring a plurality of positional parameters for each alignment mark. Based on the measured plurality of positional parameters, which are weighted with weighing coefficients, at least one parameter of the model of the object is determined. The numerical value of each weighing coefficient is determined together with the at least one parameter of the model.

Abstract: The present invention is related to a method for re-enabling transport by means of a magnetic field gradient transport mechanism of magnetic beads comprising a ligand in a solution on top of a surface comprising a receptor bound with said ligand, comprising the step of changing the properties of said solution such that dissociation occurs between said ligand and said receptor, and such that a sufficient repulsive interaction is created between said surface and said bead to allow transport of said bead.

Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.

Abstract: A method for estimating transceiver non-idealities is disclosed. In one aspect, the method comprises generating a preamble comprising multiple sets of known training sequences with a synchronization part preceding an estimation part. The training sequences in the estimation part comprises at least two sequences which are (i) complementary Golay sequence pairs and (ii) selected to satisfy a predetermined correlation relationship chosen for estimation of a first non-ideality characteristic. A first estimate of a non-ideality characteristic is determined on the basis of the known training sequences of the synchronization part of the received preamble. The estimation part of the received preamble is compensated by this estimate. Another non-ideality characteristic is determined by the compensated estimation part, exploiting the predetermined correlation relationship.

Abstract: A method of fabricating a multi-gate device is disclosed. In one aspect, the method includes providing a substrate having a first semiconductor layer with a first carrier mobility enhancing parameter, an insulating layer, a second semiconductor layer with a second carrier mobility enhancing parameter different from the first carrier mobility enhancing parameter. A first and second dielectric layer are then provided on the substrate. A first trench is formed in a first active region through the dielectric layers, the second semiconductor layer and the buried insulating layer. A first fin is formed in the first trench, protruding above the first dielectric layer and having the first carrier mobility enhancing parameter. A second trench is formed in a second active region through the dielectric layers. A second fin is formed in the second trench, protruding above the first dielectric layer and having the second mobility enhancing parameter.

Abstract: Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system as well as methods, apparatus and software products for run-time memory management techniques of such a system. Memory assignment techniques are described for assigning data to a hierarchical memory particularly for multi-tasked applications where data of dynamically created/deleted tasks is allocated at run-time. The energy consumption of hierarchical memories such as multi-banked memories depends largely on how data is assigned to the memory banks. Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system which improve a cost function such as energy consumption.

Abstract: The present disclosure is related to non-volatile memory devices comprising a reversible resistivity-switching layer used for storing data. The resistivity of this layer can be varied between at least two stable resistivity states such that at least one bit can be stored therein. In particular this resistivity-switching layer is a metal oxide or a metal nitride. A resistivity-switching non-volatile memory element includes a resistivity-switching metal-oxide layer sandwiched between a top electrode and a bottom electrode. The resistivity-switching metal-oxide layer has a gradient of oxygen over its thickness. The gradient is formed in a thermal oxidation step. Set and reset voltages can be tuned by using different oxygen gradients.

Abstract: The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device.

Abstract: One inventive aspect is related to a method of bonding two elements. The method comprises producing on a first element a first micropattern, comprising a first metal layer. The method further comprises producing on a second element a second micropattern, comprising a second metal layer. The method further comprises applying onto the first micropattern and/or on the second micropattern a layer of solder material. The method further comprises producing on at least one of the elements a patterned non-conductive adhesive layer around the micropattern on the element. The method further comprises joining the first micropattern and the second micropattern by means of a thermocompression or reflow method, wherein the producing of an adhesive layer is performed before the joining such that the first and second elements are secured to each other by the adhesive layer(s) after joining.

Abstract: One inventive aspect is related to an atomic force microscopy probe. The probe comprises a tip configuration with two probe tips on one cantilever arm. The probe tips are electrically isolated from each other and of approximately the same height with respect to the cantilever arm. The outer surface of the tip configuration has the shape of a body with a base plane and an apex. The body is divided into two sub-parts by a gap located approximately symmetrically with respect to the apex and approximately perpendicular to the base plane. Another inventive aspect related to methods for producing such an AFM probe.

Abstract: A microstructure has a substrate, a fixed electrode having a plurality of fixed fingers fixed to the substrate, a movable electrode having a body (28) and a plurality of fingers (22) extending from the body, the movable electrode being movable relative to the fixed fingers to vary a capacitance of the electrodes. The fixed fingers (21) extend in a first plane parallel to a main surface of the substrate, wherein the body of the movable electrode extends in a second plane adjacent to the first plane so that the body faces at least some of the plurality of fixed fingers. Such vertical integration can help enable such devices to be made more compact.

Abstract: A method for determining programming/erase conditions and a method for operating a charge-trapping semiconductor device are disclosed. Programming and erase conditions are determined such that a first net charge distribution variation profile, upon going from programmed to erased state, is substantially the opposite of a second net charge distribution variation profile, upon going from erased to programmed state.

Abstract: The disclosed systems and methods relate to floating gate non-volatile memory cells, with a floating gate comprising at least two layers constructed in different conductive or semiconductive materials.

Abstract: A method of forming a quantum system comprising computational elements, consisting of an insulated ring of superconductive material, and semi-closed rings, which are used as an interface or input/output facility between the quantum bit and the external world, is disclosed. Faraday induction is used to provide electromagnetic coupling between adjacent computational elements and between the computational elements with interface elements of the quantum system. Therefore the corresponding magnetic flux acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements of the quantum system.

Abstract: A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method comprises providing a first metal layer over a first electrode in a first region, and at least a first work function tuning element. The method further comprises providing a second metal layer of a second metal in a second region at least over a second electrode. The method further comprises performing a first silicidation of the first electrode and a second silicidation of the second electrode simultaneously.

Abstract: A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.

Abstract: A method for forming at least one quantum dot at least one predetermined location on a substrate is disclosed. In one aspect, the method comprises providing a layer of semiconductor material on an insulating layer on the substrate. The layer of semiconductor material is patterned so as to provide at least one line of semiconductor material having a width (wL) and having a local width variation at least one predetermined location where the at least one quantum dot has to be formed. The local width variation has an amplitude (A) of between about 20 nm and 35 nm higher than the width wL of the at least one line. The at least one line is patterned to form at least one quantum dot. A design for a lithographic mask for use with the method and a method for making such a design are also disclosed.