Abstract: An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.
Type:
Grant
Filed:
April 25, 2002
Date of Patent:
August 31, 2004
Assignee:
Interuniversitair Micoroelektronica Centrum (IMEC,
vzw)
Abstract: A method for detecting breakdown in a dielectric layer. The method includes applying a signal to the dielectric layer, measuring a plurality of sets of readings having values, which are in relation to the signal, searching and identifying outlier readings in each of the sets, the outlier readings being defined by the fact that they have values which are significantly higher or lower than the majority of the values of the set, selecting from each of the sets, one reading which is not one of the outlier readings, and comparing the value of the one selected reading to a reference value, so that the exceeding of the value leads to the conclusion that a predefined probability is present for having a breakdown state in the layer.
Type:
Grant
Filed:
April 22, 2002
Date of Patent:
August 17, 2004
Assignee:
Interuniversitair Microelektronica Centrum (IMEC, vzw)
Inventors:
Philippe Roussel, Robin Degraeve, Geert Van den Bosch
Abstract: A loop transformation step, to be performed on code and improving data transfer and storage, while executing said transformed code on a parallel processor, is disclosed. Improval of the data locality and regularity of the algorithm, described by said code, is aimed at. Said loop transformation step works globally and is feasible for realistic code sizes.
Type:
Grant
Filed:
January 31, 2000
Date of Patent:
August 3, 2004
Assignee:
Interuniversitair Microelektronica Centrum (IMEC) vzw
Abstract: Methods and architectures for turbo decoding are presented. The methods are such that low energy consumption is obtained with reduced memory requirements. Moreover the methods show improved performance with respect to latency.
Type:
Grant
Filed:
January 28, 2003
Date of Patent:
July 6, 2004
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Inventors:
Jochen Uwe Giese, Curt Schurgers, Liesbet Van der Perre, Bert Gyselinckx, Francky Catthoor, Marc Engels
Abstract: An apparatus for receiving and/or transmitting signals using orthogonal frequency division multiplexing, said apparatus being adapted for outputting a first output signal, comprising:
a time synchronisation circuit, being adapted for determination of control information from a first signal, said first signal comprising at least of a first part being a non-orthogonal frequency division multiplexing signal and a second part being an orthogonal frequency division multiplexing signal, said determination of control information exploiting said first part of said first signal;
said time synchronisation circuit, further being adapted for converting said second part of said first signal into a second signal, being in time domain representation;
a transformation circuit at least converting said second signal into a third signal, being in frequency domain representation;
a first frequency domain circuit, at least converting said third signal into said first output signal; and
said second signal and said second part
Type:
Grant
Filed:
February 16, 2000
Date of Patent:
July 6, 2004
Assignees:
IMEC, SAIT Devlonics
Inventors:
Wolfgang Eberle, Liesbet Van der Perre, Steven Thoen, Bert Gyselinckx, Mark Engels
Abstract: A full metal probe and a method of making the metal probe for electrical atomic force microscopy. In one embodiment, the method comprises manufacturing the full metal probe using two lithography steps. The step of etching thin membranes is dropped or eliminated to substantially reduce the processing time. Thus, topside processing is sufficient. The probe and tip can be peeled off from the wafer using a metallization procedure.
Type:
Grant
Filed:
September 12, 2001
Date of Patent:
June 29, 2004
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: The present invention is related to an Electrostatic Discharge protection device. This may be a semiconductor device such as a CMOS transistor, having a snap-back IV characteristic, in order to withstand ESD pulses. The device of the invention comprises an additional doped region, which influences the internal resistance of the substrate whereupon the device is built. This has a positive effect on the snap-back characteristic, putting the snap back trigger voltage and current at a lower value, compared to prior art devices.
Type:
Application
Filed:
August 29, 2003
Publication date:
June 24, 2004
Applicant:
Interuniversitair Microelektronica Centrum (IMEC)
Inventors:
Vesselin K. Vassilev, Guido Groeseneken
Abstract: The present invention is related to a photovoltaic device, the device comprising a first layer of a first semiconductor material of a first conductivity type, a second layer of a second semiconductor material of the opposite conductivity type of the first layer, and a third layer of a third porous semiconductor material situated between the first layer and the second layer. The present invention also provides a method for producing the photovoltaic device.
Type:
Application
Filed:
September 8, 2003
Publication date:
June 3, 2004
Applicants:
Interuniversitair Microelektronica Centrum (IMEC), FernUniversitat Hagen
Inventors:
Renat Bilyalov, Alexander Ulyashin, Jef Poortmans, Wolfgang Fahrner
Abstract: The present invention provides a method of transfer of a first planar substrate with two major surfaces to a second substrate, comprising the steps of forming the first planar substrate, attaching one of the major surfaces of the first planar substrate to a carrier by means of a release layer attaching the other major surface of the first substrate to the second substrate with a curable polymer adhesive layer partly curing the polymer adhesive layer, disconnecting the release layer from the first substrate to separate the first substrate from the carrier, followed by curing the polymer adhesive layer.
The method may be used to form a stack of dies (4, 14 . . . ) which are adhered together by cured polymeric layers (7, 17). Each die (4, 14 . . . ) may include a device layer and an ultra-thin substrate manufactured and assembled by the method described above.
Type:
Grant
Filed:
July 25, 2002
Date of Patent:
May 4, 2004
Assignees:
Imec VZW, Alcatel
Inventors:
Eric Beyne, Augustin Coello-Vera, Olivier Vendier
Abstract: A level-shifter architecture with high-voltage driving capability and extremely low power consumption, exploiting dynamic control of the charge on the gate electrodes of the high-voltage output transistors, is provided. The architecture can be integrated in CMOS technology and can be applied to various applications, including monolithic integration of high-voltage display driver circuits in battery-powered applications.
Type:
Grant
Filed:
September 22, 2000
Date of Patent:
May 4, 2004
Assignees:
Interuniversitar Micro-Elektronica Centrum (IMEC vzw), Universiteit Gent, Asulab S.A.
Abstract: An exemplary method for depositing a layer on a surface of a dielectric layer where the dielectric layer contains an organic material comprises exposing the surface of the dielectric layer to a substance, such as a substance containing nitrogen. This exposure modifies, at least, the exposed surface of the dielectric layer. The method further includes depositing a layer, such as a barrier layer, using an atomic layer deposition process on the exposed surface of the dielectric layer. In certain embodiments, exposure of the wafer to the substance containing nitrogen result in a first region of the dielectric having a first concentration of nitrogen incorporated and a second region having a second amount of nitrogen incorporated in the dielectric layer, the second concentration being higher greater than the first concentration.
Type:
Application
Filed:
August 15, 2003
Publication date:
April 15, 2004
Applicant:
Interuniversitair Microelektronica Centrum (IMEC VZW)
Inventors:
Jorg Schuhmacher, Ana Martin Hoyas, Marc Schaekers, Serge Vanhaelemeersch
Abstract: A shielded interconnect and a method of manufacturing a shielded interconnect implemented in a damascene back-end-of-line technology to form electromagnetically shielded interconnects. The standard metallization of the damascene technology is used as a core layer in a coaxial interconnect line. Prior to filling the via and trench openings in the damascene stack with this standard metallization, conductive and dielectric layers are formed as shield and insulator layers, respectively, of the coaxial interconnect line.
Type:
Grant
Filed:
September 6, 2001
Date of Patent:
April 13, 2004
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Inventors:
Michele Stucchi, Karen Maex, David De Roest
Abstract: A method of etching a semiconductor substrate is described, the method comprising the steps of applying a paste containing an etchant to the substrate, and carrying out a thermal processing step to etch a part or a layer of the substrate where the paste has been applied. The etchant paste is preferably a caustic etching paste. The etchant paste may be applied selectively to a major surface of the substrate to form a pattern of applied paste. For example, the paste may be applied by a printing method, such as screen-printing. The method may be used to produce solar cells.
Type:
Application
Filed:
June 27, 2003
Publication date:
April 1, 2004
Applicant:
Interuniversitair Microelektronica Centrum (IMEC)
Inventors:
Jozef Szlufcik, Emmanuel Van Kerschaver, Christophe Allebe
Abstract: Structures and methods are disclosed to produce mechanical strength in Micro Electro Mechanical Systems by increasing the moment of inertia of some of the composing elements. In one aspect, a thermal sensor with improved mechanical strength, thermal insulation and time constant is achieved. Moreover, the current method and apparatus is advantageous in terms of process time and process cost, particularly in the area of lithographic patterning.
Type:
Grant
Filed:
March 23, 2001
Date of Patent:
March 16, 2004
Assignee:
Interuniversitair Microelektronica Centrum (IMEC VZW)
Abstract: A method and apparatus for removing a first liquid from a surface of a substrate is provided. A second liquid is supplied to at least part of a surface of a substrate having a rotary movement. The rotary movement has a center of rotation and an edge of rotation. The second liquid is directed from the center of rotation to the edge of rotation using a nozzle. A dry zone is created on the substrate as the position of the spray moves from the center of rotation to the edge of rotation. As a result, the first liquid and the second liquid are removed from the surface of the substrate.
Type:
Application
Filed:
May 6, 2003
Publication date:
March 11, 2004
Applicant:
IMEC vzw
Inventors:
Frank Holsteyns, Marc Heyns, Paul W. Mertens
Abstract: Dielectric material compositions comprising HfO2 and a second compound are disclosed. The compositions are characterized by at least a part of the compositions being in a cubic crystallographic phase. Further, semiconductor based devices comprising such dielectric material compound and method for forming such compounds are disclosed.
Type:
Application
Filed:
June 10, 2003
Publication date:
February 12, 2004
Applicant:
Interuniversitair Microelektronica Centrum (IMEC vzw)
Abstract: An atomic force microscopy (AFM) probe and a method of manufacturing mounted probes for AFM applications. The method implements an optimized soldering procedure for mounting a probe to a holder chip. In one embodiment, a metallisation system of Ti:W+Ni+Au is applied with a SnBi58 solder paste in combination with a hotplate. The mechanical connection between the probe and holder chip is preferably rigid. The soldered probe is highly conductive and the probe-holder chip assembly shows clear resonance peaks in tapping mode AFM.
Type:
Grant
Filed:
September 14, 2001
Date of Patent:
February 10, 2004
Assignee:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: The invention presents video information stream encoding methods used in applications of a data storage and transfer design methodology for data-dominated applications. The invention relates to video encoding methods with variable video frames designed such that the digital system on which the methods are implemented, consumes a minimal of power, during their execution and still obtain excellent performance such as speed compliance. The resulting video information stream encoding methods can be mapped on different processor architectures and custom hardware. The methods enable combined low power consumption, reduced bus loading and increased performance to achieve speed compliance. The encoding methods are essentially based on block-based motion estimation and grouping of motion estimations of various video frames.
Type:
Grant
Filed:
March 3, 1999
Date of Patent:
February 10, 2004
Assignee:
Interuniversitair Micro-Elektronica Centrum (IMEC vzw)
Abstract: The present invention is related to a device suitable for the preparation of a sensor, comprising a substrate comprising a metal layer, the metal layer comprising at least a first region wherein to a first region is attached a first species comprising a compound of chemical formula:
Type:
Application
Filed:
June 3, 2003
Publication date:
January 29, 2004
Applicant:
Interuniversitair Microelektronica Centrum (IMEC)
Abstract: The present invention is related to a thin-film opto-electronic device and a method of fabricating the same. Particularly this thin film opto-electronic device is fabricated on a Si-containing substrate. The thin-film material is a crystalline semiconductor material. In order to increase the efficiency of this device a porous silicon layer is applied between the thin-film and the substrate. This porous silicon layer has both light reflecting and light diffusing properties thereby giving rise to light confinement in the thin-film.