Abstract: Example embodiments relate to fast sample loading microfluidic reactors and systems. One embodiment includes a microfluidic device. The microfluidic device includes a reaction chamber allowing reacting of at least one fluid material. The microfluidic device also includes at least two fluidic channels coupled to the reaction chamber for providing a fluid to and exiting a fluid from, respectively, the reaction chamber. Each fluidic channel includes an inlet and an outlet. Each fluidic channel is configured such that when a first fluid is provided in the reaction chamber via that fluidic channel, the first fluid exits the reaction chamber via the outlet of at least one other fluidic channel when the reaction chamber is filled, thereby preventing a second fluid from the at least one other fluidic channel, when present in the inlet, from diffusing into the reaction chamber.

Abstract: A digital radio-frequency (RF) circuitry is disclosed. In one aspect, the circuitry includes a digitally controlled amplifier configured to receive an RF input signal and a digital control signal, and to output an amplitude controlled output signal. The digitally controlled amplifier includes one or more common-source amplifying unit cells. A respective common-source amplifying unit cell includes a sources node connected to a switching circuitry controllable by the digital control signal so as to activate or deactivate the common-source amplifying unit cell. The switching circuitry comprises a first switch configured to connect the source node with a first power supply node and a second switch configured to connect the source node with a second power supply node when activating and deactivating, respectively, the common-source amplifying unit cell.

Abstract: A method for forming an interconnection structure for a semiconductor device is provided.

Abstract: An optical excitation system comprises a substrate (105) comprising at least one delivery means (104), for delivering analytes (109) into at least one region of interest (103), at least one radiation carrier (101) for directing at least one radiation beam from the at least one radiation carrier (101) into the at least one region of interest (103). The substrate (105) includes a thin lens system (120) comprising at least a first thin lens (121), for collimating radiation from the at least one region of interest (103) to a remote detection system (130). A particle sensor and sensing system comprising the excitation system are also provided, for example a modular particle sensor and modular sensing system, wherein the optical excitation system may be single use and disposable.

Abstract: A vertical isolated gate FET transistor integrated in the front end of line of a semiconductor chip is disclosed. In one aspect, the transistor includes a modified version of a buried power rail and back side TSV (through semiconductor via) connection for connecting the front end of line to a back side signal delivery network, such as a power delivery network (PDN), the PDN being arranged on the backside of the semiconductor substrate that carries the active devices of the FEOL on its front side. In contrast to standard power rail/TSV combinations, the TSV is not electrically connected to the rail, but isolated therefrom by a dielectric plug at the bottom of the rail. The TSV is isolated from the semiconductor substrate by a dielectric liner. Well regions are furthermore provided on the front side, enveloping the rail and the dielectric plug, and on the backside, surrounding the TSV and liner. On the back side, the well includes a contact area adjacent the TSV.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to FinFET transistors. In one aspect, at least three fins are arranged to extend in parallel in a first direction and are laterally separated from each other in a second direction by shallow trench isolation structures having a first fin spacing, where at least a portion of each fin protrudes out from a substrate. At least a portion of each of a first fin and a second fin of the at least three fins vertically protrude to a level higher than an upper surface of the shallow trench isolation structures. A third fin is formed laterally between the first fin and the second fin in the second direction, where the third fin has a non-protruding region which extends vertically to a level below or equal to the upper surface of the shallow trench isolation structures.

Abstract: Example embodiments relate to enhancement-mode high electron mobility transistors. One embodiment includes a method for manufacturing an enhancement-mode high electron mobility transistor. The method includes providing a stack of layers. The stack of layers includes a substrate, a III-V channel layer over the substrate, a III-V barrier layer on the channel layer, a p-doped III-V layer on the III-V barrier layer, and a Schottky contact interlayer on the p-doped III-V layer. The p-doped III-V layer has a first surface area. The Schottky contact interlayer has a second surface area. The second surface area is less than the first surface area. The second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered. The method also includes depositing a metal gate on the Schottky contact interlayer.

Abstract: The disclosure is related to a method for performing SPM measurements, wherein a sample is attached to a cantilever and scanned across a tip. The tip is one of several tips present on a substrate comprising at least two different types of tips on its surface, thereby enabling performance of multiple SPM measurements requiring a different type of tip, without replacing the cantilever. The at least two different types of tips are different in terms of their material, in terms of their shape or size, and/or in terms of the presence or the type of active or passive components mounted on or incorporated in the substrate, and associated to tips of one or more of the different types. The disclosure is equally related to a substrate comprising a plurality of tips suitable for use in the method of the disclosure.

Abstract: A microfluidic device for electrically activating a passive capillary stop valve, an apparatus and method are provided. The microfluidic device includes a first channel for containing a first fluid, and an output channel, wherein the first channel comprises a first interface with the output channel, and the first interface comprises a capillary stop valve characterised in that the microfluidic device also comprises a second channel for containing a second fluid, wherein the second channel comprises a second interface with the output channel, and the first channel and the second channel are electrically isolated from each other, and the first interface and the second interface are arranged relative to each other thereby being configured to activate fluid flow from the first channel into the output channel when a first fluid and a second fluid are present, and an electrical potential difference is applied between the first fluid and the second fluid.

Abstract: A method is provided for bonding and interconnecting two semiconductor chips arranged on semiconductor substrates. HSQ (Hydrogen Silsesquioxane) or an equivalent material is used as a bonding layer and after bonding and thinning one of the wafers (or first thinning and then bonding), the bond layer is locally irradiated by an e-beam through the thinned substrate, thereby locally transforming the bonding material into silicon oxide. Then a via opening is etched through the thinned substrate and an etch process selectively removes the oxide from an area delimited by the bonding material or vice versa. The filling of the via opening establishes an electrical connection between the bonded wafers, that is equivalent to a connection obtained by hybrid bonding, but that does not suffer from the disadvantages thereof.

Abstract: A method, system, use, and computer program product for inspection of an item are disclosed. The method (1) comprises acquiring (2) a projection image of the item using a radiation imaging system and obtaining (3) a plurality of simulated projection images of the item or a component thereof, based on a simulation of a numerical three-dimensional model, in which at least one geometric parameter relating to the relative orientation between the simulated item, a simulated radiation source, and a simulated detection plane varies over the plurality of simulated images. The method comprises determining (4) a relative orientation of the item with respect to the imaging system, said determining of the relative orientation comprises comparing (9) the projection image to the plurality of simulated images.

Abstract: The disclosed technology relates to a method of forming a stacked semiconductor device. One aspect includes fin structures formed by upper and lower channel layers which are separated by an intermediate layer. After preliminary fun cuts are formed in the fin structure, a sacrificial spacer is formed that covers end surfaces of an upper channel layer portion. Final fin cuts are formed in the fin structure where the lower channel layer is etched which defines a lower channel layer portion. Lower source/drain regions are formed on end surfaces of the lower channel layer portion. The sacrificial spacer shields the end surfaces of the upper channel layer portion allowing for selective deposition of material for the lower source/drain regions.

Abstract: The disclosed technology relates to a molecular synthesis device. In one aspect, the molecular synthesis device comprises a synthesis array having an array of synthesis locations and an electrode arranged at each synthesis locations. The molecular synthesis device further comprises a non-volatile memory having an array of bit cells and a set of wordlines and a set of bitlines. Each bit cell comprises a non-volatile memory transistor having a control gate connected to a wordline, a first source/drain terminal, and a second source/drain terminal connected to a bitline. The electrode at each synthesis locations of the synthesis array is connected to the first source/drain terminal of a corresponding bit cell of the non-volatile memory.

Abstract: The present disclosure is directed to an impedance spectroscopy system for bio-impedance measurement. The impedance spectroscopy system includes a signal generator configured to generate a signal with a broadband frequency spectrum and to generate an analog injection current from the signal with the broadband frequency spectrum. The analog injection current has a high pass frequency characteristic. The impedance spectroscopy system also includes an amplifier configured to measure a voltage signal in response to the analog injection current and to simultaneously measure a biopotential signal. Further, the impedance spectroscopy system includes a processor configured to analyze the voltage signal to derive a bio-impedance spectrum as well to derive further information from the biopotential signal.

Abstract: The present disclosure relates to devices and methods for non-invasive measuring of analytes. At least one embodiment relates to a wearable system for non-invasive measuring of a concentration of an analyte in skin tissue. The wearable system includes an integrated circuit that includes a first optical unit. The first optical unit includes a Raman spectrometer. The first optical unit also includes an OCT spectrometer and an interferometer optically coupled to the OCT spectrometer or an infrared (IR) spectrometer. The first optical unit additionally includes a light coupler. The wearable system further includes a first light source for performing Raman spectroscopy. The wearable system additionally includes a second light source for performing OCT spectroscopy or IR spectroscopy. Still further, the wearable system includes read-out electronics to determine an optical model of the skin tissue based on the spectroscopic data and to determine the concentration of the analyte.

Abstract: A three-dimensional (3D) power device having a plurality of layers that are stacked on top of each other and insulated from each other by interlayers, the plurality of layers comprising a lower layer comprising electrical and thermal conductors; a group III-Nitride based device layer formed above the lower layer, the group III-Nitride based device layer comprising at least one group III-Nitride based power device; a control layer formed above the group III-Nitride based device layer, the control layer comprising at least one control device; and a redistribution layer in between the group III-Nitride based device layer and the control layer, the current redistribution layer comprising a metal pattern being provided for laterally redistributing electrical currents and/or heat.

Abstract: Example embodiments relate to masks for extreme-ultraviolet (extreme-UV) lithography and methods for manufacturing the same. An example embodiment includes a mask for extreme-UV lithography. The mask includes a substrate. The mask also includes a reflecting structure that is supported by the substrate in a use face and is reflection-effective for extreme-UV radiation impinging onto the reflecting structure from a side opposite the substrate. Further, the mask includes attenuating and phase-shifting portions that are distributed within the use face that are suitable for attenuating and phase-shifting extreme-UV radiation parts reflected by the mask through the portions such that an upper surface of the mask in the use face, formed partly by the portions on the side opposite the substrate, exhibits height variations at sidewalls of the portions that extend perpendicular to the use face. In addition, the mask includes a capping layer that covers at least the sidewalls of the portions.

Abstract: The present disclosure relates to a method for forming a pellicle for extreme ultraviolet lithography, the method comprising: forming a coating of a first material on a peripheral region of a main surface of a carbon nanotube pellicle membrane, the membrane including a carbon nanotube film, arranging the carbon nanotube pellicle membrane on a pellicle frame with the peripheral region facing a support surface of the pellicle frame, wherein the support surface of the pellicle frame is formed by a second material, and bonding together the coating of the carbon nanotube pellicle membrane and the pellicle support surface by pressing the carbon nanotube pellicle membrane and the pellicle support surface against each other. The present disclosure relates also relates to a method for forming a reticle system for extreme ultraviolet lithography.

Abstract: An example method and hyperspectral imaging (HSI) system for imaging a scene are provided. The method is for imaging the scene with the HSI system including a sensor with a plurality of sensor pixels and a plurality of spectral filters, each of the spectral filters being associated with one of the sensor pixels. The method comprises obtaining a higher-resolution spatial image by illuminating the scene with a first set of wavelengths, wherein each spectral filter passes the first set of wavelengths to the sensor pixel it is associated with. The method further comprises obtaining a lower-resolution hyperspectral image by illuminating the scene with a second set of wavelengths, wherein each spectral filter passes only a subset of the second set of wavelengths to the sensor pixel it is associated with.

Abstract: A method includes representing dots of an image to be displayed within a field by a digital image code. The field is divided into sub-fields which are further divided into a first and second time interval which respectively comprise a first and a second number of equally long time slots. Time slots are assigned to each bit of the digital image code according to each bit's significance. Successive time slots of the first time interval are assigned to one of the bits of the image code and successive time slots of the second time interval are assigned to a different one of the bits of the image code. Within the duration of at least one sub-field, each rows is selected twice for respectively writing a first bit of the image code during the first time interval and writing a second bit of the image code during the second time interval.