Patents Assigned to IMEC
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Patent number: 8525129Abstract: The present invention relates to a gas sensing device comprising a nanoparticle layer (1) and a quantum dot layer (3) separated from each other by a gas absorption layer (2) which has a thickness which changes upon absorption of a gas. The nanoparticle layer (1) is provided for generating a surface plasmon resonance within a plasmon resonance frequency range upon illumination with light within a light frequency range; the quantum dot layer (3) has an absorption spectrum overlapping with said plasmon resonance frequency range of said nanoparticle layer (1) and shows photoluminescence in a photoluminescence emission frequency range upon absorption of energy within its absorption spectrum. The present invention further relates to a method for fabricating such a gas sensing device and to a method of using such a gas sensing device.Type: GrantFiled: December 17, 2008Date of Patent: September 3, 2013Assignee: Stichting IMEC NederlandInventors: Peter Offermans, Mercedes Crego Calama
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Patent number: 8524554Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.Type: GrantFiled: October 16, 2012Date of Patent: September 3, 2013Assignees: IMEC, Samsung Electronics Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hag-Ju Cho, Anabela Veloso, HongYu Yu, Stefan Kubicek, Shou-Zen Chang
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Patent number: 8524562Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.Type: GrantFiled: September 15, 2009Date of Patent: September 3, 2013Assignee: IMECInventors: Wei-E Wang, Han Chung Lin, Marc Meuris
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Patent number: 8518735Abstract: The present invention relates in a first aspect to methods for producing a nanofibres-containing layer for use as an active layer in an organic electronic device. The method comprising the steps of: a) first heating up a nanofibre-forming polymer in a solvent at a temperature T1, then b) cooling said solution down to a temperature T2 at a rate less than 40° C./h thereby forming a dispersion comprising crystalline nanofibres of said nanofibre-forming polymer, then c) raising the temperature of said dispersion to a temperature T3 higher than T2, but lower than said temperature T1, and then d) coating said dispersion on a substrate at said temperature T3 thereby forming a layer for use as an element of said organic electronic device, wherein before step (d), a step of adding an electron acceptor to the solution or dispersion is performed.Type: GrantFiled: December 18, 2009Date of Patent: August 27, 2013Assignees: IMEC, Universiteit HasseltInventors: Laurence Lutsen, Wibren Oosterbaan, Sabine Bertho, Dirk Vanderzande
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Patent number: 8518793Abstract: A method for forming a MIM capacitor structure includes the steps of obtaining a base structure provided with a recess, the recess exposing a conductive bottom electrode plug; selectively growing Ru on the bottom electrode plug, based on a difference in incubation time of Ru growth on the bottom electrode plug compared to the base structure material; oxidizing the selectively grown Ru; depositing a Ru-comprising bottom electrode over the oxidized Ru; forming a dielectric layer on the Ru-comprising bottom electrode; and—forming a conductive top electrode over the dielectric layer.Type: GrantFiled: October 17, 2012Date of Patent: August 27, 2013Assignee: IMECInventors: Min-Soo Kim, Christian Caillat, Johan Swerts
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Publication number: 20130214863Abstract: The present disclosure relates to a front-end system for a radio device, the front-end system comprising a low-noise amplifier (LNA), arranged for receiving a radio frequency input signal (RFIN) and arranged for outputting an amplified radio frequency signal (RFOUT), wherein the low-noise amplifier comprises a first differential amplifier, and a mixer (MIX), arranged for down-converting the amplified radio signal (RFOUT) provided by the low-noise amplifier (LNA) to a baseband signal (BB), by multiplying the amplified radio signal (RFOUT) with a local oscillator (LO) frequency tone, said low-noise amplifier (LNA) and said mixer (MIX) being inductively coupled.Type: ApplicationFiled: February 15, 2013Publication date: August 22, 2013Applicant: IMECInventor: IMEC
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Publication number: 20130214946Abstract: An ADC includes sampling means for sampling an input voltage signal, comparator(s) for receiving the sampled signal, and a DAC including circuitry for generating a search signal approximating the input signal and a calibration signal. The search signal and the calibration signal are to be applied to a comparator. The ADC also includes a search logic block for receiving a comparator output signal, for providing input to the DAC for generating the search signal, and for producing a digital output signal. Further, the ADC includes a calibration logic block for producing a control signal to control the circuitry of the DAC and including processing means for observing the output signal, for comparing the output signal with a desired output, and for compensating analogue non-idealities of the ADC. The DAC circuitry is adapted for generating the calibration signal in accordance with the control signal and with the sampled input signal.Type: ApplicationFiled: February 14, 2013Publication date: August 22, 2013Applicants: RENESAS ELECTRONICS CORPORATION, IMECInventors: IMEC, Renesas Electronics Corporation
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Publication number: 20130214947Abstract: A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal.Type: ApplicationFiled: February 15, 2013Publication date: August 22, 2013Applicants: RENESAS ELECTRONICS CORPORATION, IMECInventors: IMEC, RENESAS ELECTRONICS CORPORATION
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Publication number: 20130214870Abstract: The present disclosure relates to an injection-locked local oscillator and a method for calibrating the same. The local oscillator includes an active circuit having at least one first resonator connected to the output of the active circuit, and at least one second resonator coupled to the at least one first resonator, thereby forming at least one coupled resonator. In another aspect, the present disclosure relates to a method for calibrating a local oscillator, the calibration being a two-step calibration based mainly on power measurement.Type: ApplicationFiled: February 15, 2013Publication date: August 22, 2013Applicants: Vrije Universiteit Brussel, IMECInventors: IMEC, Vrije Universiteit Brussel
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Patent number: 8513141Abstract: The present invention provides an etching solution for revealing defects in a germanium layer, a method for revealing defects in a germanium layer using such an etching solution and to a method for making such an etching solution. The etching solution according to embodiments of the present invention is able to exhibit an etch rate of between 4 nm·min?1 and 450 nm·min?1, which makes it suitable to be used for revealing defects in a thin layer of germanium, i.e. in a layer of germanium with a thickness of between 20 nm and 10 ?m, for example between 20 nm and 2 ?m, between 20 nm and 1 ?m or between 20 nm and 200 nm.Type: GrantFiled: October 18, 2011Date of Patent: August 20, 2013Assignee: IMECInventors: Laurent Souriau, Valentina Terzieva
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Patent number: 8507337Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.Type: GrantFiled: July 6, 2009Date of Patent: August 13, 2013Assignee: IMECInventors: Roger Loo, Frederik Leys, Matty Caymax
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Patent number: 8510686Abstract: Various implementations of the invention provide for generation of a high transmission phase shift mask layout through inverse lithography techniques. In various implementations of the present invention, a set of mask data having a plurality of pixels is generated. The transmission value associated with each pixel may then be determined through an inverse lithography technique. With various implementations of the invention, the inverse lithography technique identifies an objective function, minimizes the objective function in relation to a simulation of the optical lithographic process, such that the transmission value, which is greater than 6%, may be determined.Type: GrantFiled: September 30, 2011Date of Patent: August 13, 2013Assignee: IMECInventors: Eric Henri Jan Hendrickx, Alexander V. Tritchkov, Kyohei Sakajiri
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Patent number: 8508893Abstract: An distributed electronic circuit (1), such as a transmission line or distributed amplifier, is disclosed comprising an input terminal (2), an output terminal (3), power supply lines (4,5), a sequence of sections (61, 62, 63, 64, 65), between the input terminal (2) and the output terminal (3), arranged to transfer an electrical signal from one section to another section; each section (61, 62, 63, 64, 65) comprising at least one Electro Static Discharge (ESD) protection component (9) configured to, upon occurrence of an ESD event, convey corresponding ESD currents to a power supply line (4, 5); and wherein the ESD components (9) of the respective sections (61, 62, 63, 64, 65) are selected such that, upon occurrence of an ESD event, at least one subsequent section (62, 63, 64, 65) is triggered before the first section (61).Type: GrantFiled: August 26, 2010Date of Patent: August 13, 2013Assignee: IMECInventors: Steven Thijs, Dimitri Linten
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Publication number: 20130200320Abstract: A conductive-bridge random access memory device is disclosed comprising a second metal layer configured to provide second metal cations; a layer of insulator adjacent to the second metal layer; the layer of insulator comprising a layer of first insulator and a layer of second insulator; the layer of second insulator being adjacent to the second metal layer; a first metal layer adjacent to the layer of first insulator, the first metal layer being opposite to the second metal layer; wherein the density of the layer of second insulator is higher than the density of the layer of first insulator.Type: ApplicationFiled: February 6, 2013Publication date: August 8, 2013Applicant: IMECInventor: IMEC
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Patent number: 8501604Abstract: A method of forming a doped region in a semiconductor layer of a substrate by alloying with doping elements is disclosed. In one aspect, the method includes screen printing a paste layer of doping element paste to the substrate and firing the screen printed paste layer of doping element paste, wherein a highly pure doping element layer is applied to the semiconductor layer after which the paste layer is screen printed to the doping element layer.Type: GrantFiled: June 16, 2011Date of Patent: August 6, 2013Assignee: IMECInventor: Sukhvinder Singh
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Publication number: 20130198594Abstract: Disclosed is a method for selecting a design option for a Viterbi decoder model. In some embodiments, the method includes deriving a set of design options for a Viterbi decoder model by differentiating at least one design parameter, where the at least one design parameter comprises at least a first value for a look-ahead parameter. The method further includes performing an evaluation of each design option in the set of design options in a multi-dimensional design space and, based on the evaluation of each design option, selecting a design option in the set of design options that (i) satisfies a predetermined energy efficiency constraint and (ii) yields at least a second value for the look-ahead parameter, wherein the second value is greater than the first value and satisfies a predetermined area budget.Type: ApplicationFiled: January 11, 2013Publication date: August 1, 2013Applicants: Samsung Electronics Co. Ltd., IMECInventors: IMEC, Samsung Electronics Co. Ltd.
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Publication number: 20130194577Abstract: A method for determining an active dopant concentration profile of a semiconductor substrate based on optical measurements is disclosed. The active dopant concentration profile includes a concentration level and a junction depth. In one aspect, the method includes obtaining a photomodulated reflectance (PMOR) amplitude offset curve and a PMOR phase offset curve for the semiconductor substrate based on PMOR measurements, determining a decay length parameter based on a first derivative of the amplitude offset curve, determining a wavelength parameter based on a first derivative of the phase offset curve, and determining, from the decay length parameter and the wavelength parameter, the concentration level and the junction depth of the active dopant concentration profile.Type: ApplicationFiled: January 18, 2013Publication date: August 1, 2013Applicants: Katholieke Universiteit Leuven, IMECInventors: IMEC, Katholieke Universiteit Leuven
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Publication number: 20130187669Abstract: A built-in self-calibration system and method for a micro-mirror array device, for example, operating as a variable focal length lens is described. The calibration method comprises determining a capacitance value for each micro-mirror element in the array device at a number of predetermined reference angles to provide a capacitance-reference angle relationship. From the capacitance values, an interpolation step is carried to determine intermediate tilt angles for each micro-mirror element in the array. A voltage sweep is applied to the micro-mirror array and capacitance values, for each micro-mirror element in the array, are measured. For a capacitance value that matches one of the values in the capacitance-reference angle relationship, the corresponding voltage is linked to the associated tilt angle to provide a voltage-tilt angle characteristic which then stored in a memory for subsequent use.Type: ApplicationFiled: January 21, 2013Publication date: July 25, 2013Applicant: IMECInventor: IMEC
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Publication number: 20130187113Abstract: A nonvolatile memory device is disclosed comprising a metal-to-insulator transition material thermally coupled to a Peltier element. During programming, a selected current is flowing through the Peltier element, the level thereof determining whether the temperature of the Peltier element and hence of the thermally coupled metal-to-insulator transition material decreases or increases. In response to this temperature change, the metal-to-insulator transition material will change from one electrical conduction phase to another. The memory device is read by applying current through the metal-to-insulator transition material, the current level being selected to maintain the phase of the metal-to-insulator transition material.Type: ApplicationFiled: January 18, 2013Publication date: July 25, 2013Applicants: Katholieke Universiteit Leuven, K.U. LEUVEN R&D, IMECInventors: IMEC, Katholieke Universiteit Leuven, K.U. LEUVEN R&D
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Patent number: RE44457Abstract: Methods and apparatus for adaptive encoding of at least a part of a current frame of a sequence of frames of framed data are described which operate on a block-by-block coding basis. The methods and apparatus divide at least a part of the current frame into blocks and then perform a first sub-encoding step on a block. Thereafter a second sub-encoding step is performed on the first sub-encoded block whereby the second sub-encoding step is optimized by adapting its encoding parameters based on a quantity of the first sub-encoded part of the current frame. The quantity is determined by prediction from a reference frame. Then the same steps are performed on another block of the part of the current frame. Typically, the framed data will be video frames for transmission over a transmission channel. The adaptation of the parameters for the second sub-encoding step may be made dependent upon the characteristics or limitations, e.g. bandwidth limitation, of the channel.Type: GrantFiled: November 9, 2011Date of Patent: August 27, 2013Assignee: IMECInventor: Christophe De Vleeschouwer