Abstract: A complementary logic technology is disclosed whereby a logic gate comprises at least two metal-to-insulator transition (MIT) elements and at least two thermoelectric elements, each MIT element being thermally coupled to a corresponding thermoelectric element. In logic gates, each electric signal at an input terminal of a logic gate is first converted into two complementary thermal signals, and these thermal signals in turn determine the status of the output terminal of the logic gate, thereby generating an electrical output signal inverse to the electrical input signal or an output signal which is a Boolean operation on input signals. The parallel connection(s) of thermoelectric elements of the logic gate is used to create corresponding thermal signals for each electrical input signal. The MIT elements of the logic gate are then arranged to, in response to the associated thermal signals, execute a Boolean operation.

Abstract: The present disclosure is related to a device for cooling the surface of a semiconductor device such as an integrated circuit or the like, the cooling device comprising a plurality of channels (3?) which are non-parallel to the surface to be cooled, each channel comprising a plurality of separate electrodes (5) or equivalent conducting areas arranged along the length of each channel, the device further comprising or being connectable to means for applying a voltage to the electrodes or conducting areas in each channel according to a sequence, the sequence being such that a droplet (6) of cooling liquid in a channel may be moved from one electrode to the next, thereby transporting the droplet from the top of the channel to the bottom, from where the droplet impinges on the surface to be cooled.

Abstract: A circuit for adaptive feedback equalization is disclosed. In one aspect, the circuit includes a frequency-domain feedforward filtering section and a feedback filtering section, a slicer to slice a block of equalized symbols, a summing module for summing outputs of the filtering sections thereby yielding the block of equalized symbols. First and second updating modules provide coefficient updates to the filtering sections. The updating modules are fed with a frequency-domain converted block of error signals indicating the difference between the block of equalized symbols at the slicer input and the block of sliced symbols at the slicer output and for computing updates using the frequency-domain converted block of error signals. A time-domain compensation module receives a time-domain version of the updated filter coefficients of the feedback filtering section and symbols of the block of sliced symbols. It adds a feedback error compensation signal to the block of equalized symbols.

Abstract: A dry etching method for texturing a surface of a substrate is disclosed. The method includes performing a first dry etching onto the surface of the substrate thereby forming a surface texture with spikes and valleys, the first dry etching comprising etching the surface of the substrate in a plasma comprising fluorine (F) radicals and oxygen (O) radicals, wherein the plasma comprises an excess of oxygen (O) radicals. The method may further include performing a second dry etching onto the surface texture thereby smoothening the surface texture, the second dry etching comprising chemical isotropic etching the surface texture, obtained after the first dry etching, in a plasma comprising fluorine (F) radicals, wherein the spikes are etched substantially faster than the valleys.

Abstract: A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect.

Abstract: A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 ?m and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device.

Abstract: A method of manufacturing a semiconductor device is disclosed. In one aspect, the method includes: forming a dummy gate over a substrate layer; forming first gate insulating spacers adjacent to sidewalls of the dummy gate and over the substrate layer, the first spacers having two sidewalls and two surface profiles where the sidewalls meet the substrate layer; forming a source and drain region using the surface profiles; forming second gate insulating spacers adjacent to the sidewalls of the first spacers and over the source and drain regions; removing the dummy gate and the first spacers, thereby forming a first recess; depositing a dielectric layer in the first recess along the side walls of the second spacers and over the substrate layer, thereby forming a second recess; and depositing a gate electrode in the second recess.

Abstract: An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.

Abstract: Presented is a method of managing the operation of a system including a processing subsystem configured to run a multimedia application and a telecommunication subsystem. The method includes determining telecom environment conditions, and selecting a working point from a plurality of predetermined working points. The selecting is based at least in part on the determined environmental conditions. The method also includes setting control parameters in the multimedia application and/or the telecommunication subsystem to configure the system to operate at the selected working point, and operating the system at the selected working point.

Abstract: The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.

Abstract: A method is provided for producing a LED device, comprising a stack of layers comprising a light producing layer the light producing layer not being the top or bottom layer of the stack, wherein a layer at the top or bottom of the stack is subjected to a texturization aimed at enhancing the light extraction efficiency of the LED, wherein the texturization comprises the step of producing on the top or bottom surface a plurality of surface features, the surface features being arranged according to a pattern defined by starting from a regular pattern of features and subjecting each feature of the regular pattern to a deviation from the location in the regular pattern, the deviation being in a random direction and/or having a random amplitude. According to another embodiment, a random deviation is applied to one or more dimensions of the features in the regular pattern.

Abstract: A method for measuring a concentration of a biogenic substance in a living body includes steps of: preparing an apparatus including a light source, a substrate which has periodic metal structures and generates surface enhanced Raman scattering light by being irradiated with light from the light source, and spectroscopic means which disperses and detects the light, wherein the periodic metal structure is arranged with first and second distances in first and second direction respectively, the first distance is set to generate surface plasmon by matching a phase of the light from the light source, and the second distance is smaller than the first distance and is set between 300 nm and 350 nm; irradiating the substrate with the light from the light source to generate the surface enhanced Raman scattering; detecting the scattering with the spectroscopic means; and calculating the concentration of the biogenic substance based on the scattering.

Abstract: A metal nanoantenna for use in a biosensing device is disclosed. The metal nanoantenna is arranged to exhibit at least two particle plasmon resonances or surface plasmon resonances (SPRs). The nanoantenna is for use in a sensor and allows detection at low concentration of biological components. In one aspect, the nanoantenna can have an asymmetric structural configuration and spectrally separated resonances. In one aspect, there is a location in its structure providing local electromagnetic field enhancement at all of the SPRs. The metal nanoantenna can be used for background free measuring of a quantity of a biological component.

Abstract: An atomic force microscopy probe configuration and a method for manufacturing the same are disclosed. In one aspect, the probe configuration includes a cantilever, and a planar tip attached to the cantilever. The cantilever only partially overlaps the planar tip, and extends along a longitudinal direction thereof. The planar tip is of a two-dimensional geometry having at least one corner remote from the cantilever, which corner during use contacts a surface to be scanned.

Abstract: A programmable device suitable for software defined radio terminal is disclosed. In one aspect, the device includes a scalar cluster providing a scalar data path and a scalar register file and arranged for executing scalar instructions. The device may further include at least two interconnected vector clusters connected with the scalar cluster. Each of the at least two vector clusters provides a vector data path and a vector register file and is arranged for executing at least one vector instruction different from vector instructions performed by any other vector cluster of the at least two vector clusters.

Abstract: The disclosure relates to an n-channel laterally diffused metal-oxide-semiconductor device comprising an n+ source (11) in a p-well region (12) and an n+ drain (21) in an n-well region (22), an n-channel (14) extending between the n+ source (11) and the n-well region (22), and a poly gate (3) having a first part (31) above the channel and spanning the entire channel and a second part (32) extending above a part (24) of the n-well region (22) for forming a gate-to-n-well-overlap. The poly gate (3) is a hybrid n+/p+ structure wherein the first part (31) is an n+ part and the second part (32) is a p+ part.

Abstract: A tunnel Field Effect Transistor is provided comprising an interface between a source and a channel, the source side of this interface being a layer of a first crystalline semiconductor material being substantially uniformly doped with a metal to the solubility level of the metal in the first crystalline material and the channel side of this interface being a layer of this first crystalline semiconductor material doped with this metal, the concentration decreasing towards the channel.

Abstract: An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.

Abstract: The present invention provides a resistive memory array arranged in a 3D stack comprising a plurality of resistivity switching memory elements laid out in an array in a first and second direction, and stacked in a third direction, a plurality of first electrodes and a plurality of second electrodes extending in the first direction, each first electrode and each second electrode being associated with the at least one resistivity switching memory element, and a plurality of transistor devices, each transistor device being electrically coupled to one of the resistivity switching memory elements, an inversion or accumulation channel of a transistor device being adapted for forming a switchable resistivity path in the third direction, between the electrically coupled resistivity switching memory element and the associated second electrode, wherein the memory array furthermore comprises at least one third electrode provided in a trench through the stack.

Abstract: A method and system are described for performing extreme ultraviolet photolithographic processing. The method comprises obtaining a substrate comprising a hard mask and a patterned layer of extreme ultraviolet (EUV) photoresist formed above the hard mask, encapsulating the patterned layer of EUV photoresist by forming an encapsulating layer being one of a silicon-oxide, silicon-nitride, silicon-oxynitride, germanium-oxide, germanium-nitride, germanium-oxynitride, silicongermanium-oxide, silicongermanium-nitride, silicongermanium-oxynitride layer on the photoresist and dry etching of the substrate for patterning the hard mask. The encapsulation layer thereby is formed at a temperature below the weakening temperature Tg of the EUV photoresist by using a first precursor being one of the group of silicon-tetrahalogenide, silicon tetrahydride, germanium-tetrahalogenide, germanium tetrahydride, silicongermanium-tetrahalogenide or silicongermanium tetrahydride precursor and an oxygen precursor.