Abstract: A circuit (10) includes a circuit input (12), a circuit output (16) and a one or more delay elements (22) positioned between the circuit input (12) and the circuit output (16). The delay elements (22) each include a differential input pair (234), a latch stage (236) and a delay controller (244A1, 244A2, 244B1, 244B2). The delay controller (244A1, 244A2, 244B1, 244B2) selectively apportions current between the differential input pair (234) and the latch stage (236) to achieve a desired delay value for the circuit (10). The circuit (10) can also include a feedback loop (18) that calibrates a DC offset of the delay elements (22). The delay elements (22) can include two or more sets of resistive loads (238A, 238B) and a rate controller (241). The rate controller (241) controls an on/off state of the resistive loads (238A, 238B) to selectively switch between full resistance and half resistance.

Abstract: A method and apparatus for selective packet discard have been disclosed where two bits are added to a packet to indicate various discard options.

Abstract: A serial display interface such as the VESA-Display Port interface is expanded to support daisy chained coupling of one display monitor to the next. Each daisy chain wise connectable display monitor has a local daisy chain transceiver device associated with it where the local transceiver device selectively picks off passing through video data streams in response to embedded MDID identification signals and forwards the selectively picked off data to the local monitor. The local transceiver device also relays the passing through video data streams on to more downstream devices of the daisy chain. In one embodiment, the daisy chain wise connectable display monitors are hot-pluggable and unpluggable.

Abstract: A computer audio system includes an audio codec and a lone controller. The audio codec is operably coupled to receive audio information, which includes tone control settings, PCM digital audio inputs and PCM digital audio outputs. In addition, the audio codec may receive audio information as analog input signals via a line-in, a CD input, or an auxiliary input. Based on the audio information, the audio codec provides a first stereo output, a second stereo output and a monotone audio output. The tone controller is operably coupled to the audio codec and includes a low pass filter, a high pass filter, a band pass filter, and a summing module. The low pass filter is operably coupled to filter the monotone audio output and isolates bass components of the audio signal being processed. By further coupling a volume control module to the low pass filter, the bass component of the audio signal being processed may be varied.

Abstract: In PCI-Express and alike communications systems, number of lanes used per channel or port can vary as a result of negotiated lane aggregation during network bring-up. Disclosed are systems and methods for efficiently realigning packet data and stripping out control bytes in a by-eight port configuration as the packet data ingresses from the physical layer (PL), past the data link layer (DL) and into the transaction layer (TL). It is shown that data routing can be reduced to just two, mux-selectable permutations based on whether the STP (start of packet) character arrives in an even numbered double-word side (DW0) or an odd-numbered double-word side (DW1) of a physical layer register.

Abstract: An audio codec includes an input for receiving audio information. Audio processing circuitry produces a first stereo audio signal, a second stereo audio signal, and a monotone audio signal based on the audio information. A low pass filter filters the monotone audio output, wherein the low pass filter passes a bass component of the monotone audio signal substantially unattenuated and attenuates higher frequency components of the monotone audio signal. A high pass filter filters the first stereo audio output, wherein the high passes filter passes a treble component of the first stereo audio signal substantially unattenuated and attenuates lower frequency components of the first stereo audio signal. A band pass filter filters the second stereo audio output, wherein the band pass filter passes a mid band component of the second audio signal substantially unattenuated and attenuates low frequency components and high frequency components of the second stereo audio signal.

Abstract: A multi-queue FIFO memory device that uses existing pins of the device to load a desired number of queues (N) into a queue number register is provided. The queue number register is coupled to a queue size look-up table (LUT), which provides a queue size value in response to the contents of the queue number register. The queue size value indicates the amount of memory (e.g., the number of memory blocks) to be included in each of the N queues. The queue size value is provided to a queue start/end address generator, which automatically generates the start and end address associated with each queue in response to the queue size value. These start and end addresses are stored in queue address register files, which enable proper memory read/write and flag counter operations.

Abstract: A controller, power converter, and a related method for secondary side control of a switch are disclosed herein. An embodiment of the present invention includes a controller. The controller comprises a drain to source voltage (VDS voltage) input configured to receive the VDS voltage of a transistor, a gate drive output configured to output a gate drive voltage to a gate of the transistor, and control logic configured to initiate a minimum on time signal independent of triggering the gate drive voltage to activate the transistor. A related method comprises comparing a VDS voltage of a transistor to a plurality of voltage threshold levels, driving a gate of the transistor when the VDS voltage crosses a predetermined voltage threshold, and asserting a minimum on time signal when the VDS voltage crosses another predetermined voltage threshold independent of driving the gate of the transistor.

Abstract: A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.

Abstract: Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each of a repeating accumulation count to generate a first domain accumulation. The first domain accumulation is sampled in a second clock domain after a time delay to generate a second domain accumulation. The time delay ensures proper setup and hold time parameters for the second clock domain relative to the first clock domain. A differentiator generates output information in the second clock domain by delaying the second domain accumulation and subtracting the delayed second domain accumulation from the second domain accumulation. The systems and methods preserve temporal characteristics of the input information in the first clock domain when it is transferred to the second clock domain as the output information.

Abstract: A serial buffer monitors an incoming stream of packets to identify single missing packets and multiple consecutive missing packets. Upon detecting multiple consecutive missing packets, an interrupt is generated, thereby stopping the data transfer. Upon detecting a single missing packet, a single missing packet identifier is inserted into the packet header of the packet that resulted in identification of the single missing packet. The incoming packets, including any inserted single missing packet identifiers, are written to a queue. When the water level reaches the water mark of the queue, the stored packets are read to create an outgoing packet stream. When a packet read from the queue includes an inserted single missing packet identifier, a dummy packet (e.g., a packet having a data payload of all zeros) is inserted into the outgoing packet stream. As a result, real-time applications are capable of processing the outgoing packet stream in a constant fashion.

Abstract: Level shifting circuits and related methods are disclosed herein. The level shifting circuit includes a cross-coupled pull-up circuit coupled to a higher supply voltage, an output signal, and an inverted output signal. An input signal transitions between a ground and a lower supply voltage and an inverted input signal transitions in a direction opposite from the input signal between the ground and the lower supply voltage. A first n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the output signal, and a source coupled to the inverted input signal. A second n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the inverted output signal, and a source coupled to the input signal. The level shifting circuit may be included in an IC with core logic in a first voltage domain and input/output logic in a second voltage domain.

Abstract: Physical layouts of integrated circuits are provided, which may include an analog-to-digital converter including a plurality of comparators. Individual transistors of each comparator of the plurality are arranged in a one-dimensional row in a first direction. Neighboring comparators of the plurality of comparators are positioned relative to each other in an abutting configuration in a second direction orthogonal to the first direction. The plurality of comparators may include multiple, inter-coupled outputs. Such an ADC may be called a Benorion Analog-to-Digital Converter. A method for fabricating an integrated circuit is also provided.

Abstract: An integrated circuit 2 includes a serial data transmitter 12 and a serial data receiver 14. A signal amplitude distorting circuit 30 is provided to introduce distortion in the amplitude of a serial data signal generated by the serial data transmitter 12 and looped back to the serial data receiver 14 so as to stress test the serial data receiver 14.

Abstract: An integrated circuit is provided comprising: a serial transmitter, a serial receiver and a serial connection providing communication between the serial transmitter and the serial receiver. The integrated circuit further comprises a duty cycle distortion circuit so that the integrated circuit can be stress tested by distorting the duty cycle of a signal within the integrated circuit.

Abstract: A system and method for efficient computation in the course of locating a position on the face of a touch-screen-equipped display device by limiting the amount of computations to weighted vectors within a range substantially less than the entire range of data input from the touch screen sensors.

Abstract: A packet switch includes a flow control circuit for preventing a downstream ingress port of the packet switch from providing a non-posted packet to an upstream egress port of the packet switch when a downstream egress port of the packet switch is congested. As a result, congestion is reduced in the downstream egress port. Additionally, congestion is reduced in an upstream ingress port of the packet switch that receives completion packets in response to non-posted packets output from the upstream egress port and provides the completion packets to the downstream egress port. Because congestion is reduced in the upstream ingress port, latency is reduced for a completion packet received at the upstream ingress port and provided to another downstream egress port of the packet switch in response to a non-posted packet provided from another downstream ingress port to the upstream egress port and output from the packet switch.

Abstract: A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses signal samples resulting from analog to digital conversion of an analog signal received via an antenna. The RF unit transfers the compressed signal samples over the serial data link to the base station processor where they are decompressed prior to the normal signal processing operations. For the downlink, the base station processor compresses signal samples and transfers the compressed signal samples over the serial data link to the RF unit. The RF unit decompresses the compressed samples and converts the decompressed samples to an analog signal for transmission over an antenna. Compression and decompression can be incorporated into operations of conventional base stations and distributed antenna systems.

Abstract: An integrated circuit (342) that is electrically connected to a printed circuit board (246) with a package substrate (344) includes a circuit body (352), and a bump array (354) that electrically connects the circuit body (352) to the package substrate (244). The bump array (354) includes a first bump set (356) having a plurality of signal bumps (364) and a plurality of non-signal bumps (366) alternatingly interspersed and aligned along an axis. With the present design, the bump array (354) allows each signal bump (364) to be surrounded by a power bump (370) and a ground bump (368). The package substrate (344) includes (i) a package body (372); and (ii) a pin array (374) that includes a first pin set (376) that includes a plurality of signal pins (384) and a plurality of non-signal pins (386) alternatingly interspersed and aligned along an axis.

Abstract: A clock signal generator includes a phase-lock loop for generating an imaging clock signal having a frequency based on a reference clock signal. The imaging clock signal generator also includes a modulation circuit for determining a number of pixels in a horizontal line of an image to be generated based on the imaging clock signal. The modulation circuit generates a modulation signal based on the determined number of pixels and the clock signal generator spreads the frequency of the imaging clock signal across a frequency range based on the modulation signal. In this way, the clock signal generator reduces electromagnetic interference in the imaging clock signal. In further embodiments, the clock signal generator generates an adjustment signal for adjusting the frequency range based on the frequency of the reference clock signal and the frequency of the imaging clock signal.