Abstract: A circuit for an N-bit stage (110i) of a pipeline ADC having L=2N levels, the circuit comprising: an operational amplifier (420); a first feedback capacitor (Cf1) having a first plate connected to an input of the operational amplifier and a second plate switchably connected on a first clock signal (?1) to a first input voltage (±Vm) and on a second clock signal (?2) to an output of the operational amplifier; a second feedback capacitor (Cf2) having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a discharge connection and on the second clock signal (?2) to an output of the operational amplifier; and a plurality of K sampling capacitors (Cu), each sampling capacitor having a first plate connected on the first clock signal to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a second input voltage (Vin) and on the second clock signal to one of a positive and negative r

Abstract: A method and apparatus for predictive switching an output have been disclosed.

Abstract: In PCI-Express and alike communications systems, data bandwidth per channel can vary as a result of negotiated port aggregation and/or bifurcation during network bring-up. Disclosed are systems and methods for opportunistically interleaving dispatches of packet data for secondary egress channels when the data bandwidth of a primary egress channel is relatively small and thus creates slack on a dispatch bus between dispatches of primary data blocks.

Abstract: Soft start circuits for a switching power converter include an amplifier configured to operate from a common bias node and amplify a difference between a positive input and a negative input to generate an amplifier output. A soft start bias circuit supplies a soft start bias current during a soft start process for the switching power converter. An operational bias circuit supplies an operational bias current after the soft start process. In some embodiments, a capacitor is operably coupled to the amplifier output and is configured to provide a frequency compensation for the switching power converter and a charging ramp for the soft start process. In some embodiments, the soft start circuit is configured such that the soft start bias current is at least an order of magnitude smaller than the operational bias current and limits a current that the amplifier can during the soft start process.

Abstract: Methods of forming packaged microelectromechanical resonators include forming a first isolation trench in a first surface of a capping substrate, with the first isolation trench encircling a first portion of the capping substrate. The first isolation trench is filled with an electrically insulating material. The first surface of the capping substrate is bonded to a device substrate, which includes the microelectromechanical resonator and at least a first electrically conductive line connected to the microelectromechanical resonator. A second surface of the capping substrate is planarized for a sufficient duration to thereby expose the electrically insulating material and the first portion of the capping substrate encircled by the first isolation trench. The exposed first portion of the capping substrate is selectively etched to thereby define a through-substrate opening therein, which exposes a first portion of the first electrically conductive line.

Abstract: A peripheral component interconnect express (PCIe) switch includes non-transparent endpoints, each of which is associated with a bus hierarchy domain. A source non-transparent endpoint in a source bus hierarchy domain receives a packet including a destination address and identifies a destination bus hierarchy domain including a destination non-transparent endpoint based on the destination address. Further, the source non-transparent endpoint translates a requester identifier in the packet to a translated requester identifier and generates a translated request packet including the translated requester identifier. The PCIe switch routes the translated request packet to the destination non-transparent endpoint through a non-transparent interconnect in the PCIe switch. In this way, the PCIe switch interconnects multiple bus hierarchy domains and is non-transparent in the multiple bus hierarchy domains.

Abstract: An inductive wireless power transfer system comprises a transmitter configured to generate an electromagnetic field to a coupling region in response to an input signal. The inductive wireless power transfer control logic is configured to determine an input power of the input signal. The control logic is configured to determine a presence of a foreign object within the coupling region in response to a comparison of the input power and an output power of an output signal of a receiver within the coupling region. Related inductive wireless power transfer systems and methods for detecting a foreign object in an inductive wireless power transfer coupling region of an inductive wireless power transfer system are disclosed.

Abstract: A method of transmitting audio data across a digital interface is provided. The method includes receiving audio data, organized as a plurality of audio samples. At least one of the plurality of audio samples may be placed into a data packet. The data packet may be transmitted during a valid transmission interval if the data packet is full or during a valid transmission interval in response to receiving a packet send event.

Abstract: A method and apparatus for A Low Power AC On-Die-Termination (ODT) Circuit using active components reduces receiver power consumption.

Abstract: A charging converter includes a plurality of switches configured to switchably operate to either step up an input voltage or step down the input voltage and generate a charging voltage on a second terminal to charge to a rechargeable storage unit, and control logic configured to operate the plurality of switches in one of a step up mode and a step down mode based on a determination of a voltage level of the input voltage relative to the desired charging voltage. A method includes determining a desired charging voltage to charge a rechargeable storage unit, switchably controlling a charging converter to step up the input voltage if an input voltage is lower than the desired charging voltage to generate a charging voltage, and switchably controlling the charging converter to step down the input voltage if the input voltage is higher than the desired charging voltage to generate the charging voltage.

Abstract: An arbiter for a space switch comprising a two buffers, a media access controller having data outputs coupled to the two buffers, and two control outputs coupled to respective buffers for buffering input data at a clock rate one-half that of the input data and a switch fabric connected to the two buffers for matching buffer data throughput with switch data throughput, the arbiter comprising first and second schedulers, each scheduler includes a plurality of inputs for connection to the two buffers for receiving requests, a plurality of outputs for granting requests and a plurality of inter connections to each of the plurality of schedulers for informing them of grants and logic for logically grouping input ports associated with a bifurcate input port, logically grouping output ports associated with a bifurcate output port, establishing round robin pointers for each of two alternate clock ticks for tracking next allowable requests and on one clock tick allowing connection requests from input ports to output po

Abstract: A packet switch includes a pipeline scheduler for scheduling packets according to a credit-based flow control protocol. A credit update pipeline stage initializes available credits for egress ports of the packet switch. A request pipeline stage generates packet requests for packets based on the available credits. A grant pipeline stage selects packets based on the ports requests and the available credits, and generates port grants for the selected packets. Additionally, the credit update stage updates the available credits based on the port grants. The packet switch routes the selected packets from ingress ports of the packet switch to the egress ports based on the port grants. In some embodiments, ingress ports generate enqueue requests based on the packets, an enqueue pipeline stage generates enqueue states based on the enqueue requests, and the request pipeline stage selects packets for routing based on the enqueue states and the available credits.

Abstract: An integrated circuit is disclosed to bypass transients between first and second nodes. The circuit includes a first bypass capacitor implemented as a metal oxide semiconductor (MOS) transistor and coupled to a first node; and a switch coupled to the first bypass capacitor and the second node, the switch preventing leakage current from passing through the first bypass capacitor during power down.

Abstract: An electronic appliance including a processor and a computer-readable medium, having instructions for execution by a processor is provided. The instructions causing the processor to perform methods to obtain an error map for locations in a touch sensor. The method including inputting a geometry for a touch sensor layout; inputting coordinates for centroids of sensing elements in the touch sensor layout; and inputting a touch geometry. The method includes the steps of selecting a plurality of test points on the touch sensor layout; generating, a calculated touch location for each of the plurality of test points; and an error map from the calculated touch locations and the test points. The method may include generating an error measure from the error map; displaying, the generated error map and the generated error measure; and adjusting the geometry for the touch sensor layout if the error measure is larger than a tolerance value.

Abstract: A method and apparatus for placing quartz SAW (Surface Acoustic Wave) devices together with a clock/oscillator have been disclosed. Mounting on a single lead frame both a SAW device and an integrated circuit (IC).

Abstract: In various embodiments, a data correction system has a data path including search modules. Each of the search modules has a respective bit error capacity for locating a number of data bit errors in a data unit based on a locator polynomial. The data correction system generates a syndrome based on an input data unit, generates a locator polynomial based on the syndrome, and determines a number of data bit errors in the input data unit based on the locator polynomial. Additionally, the data correction system selects one of the search modules having a bit error capacity of at least the number of data bit errors in the input data unit. The selected search module generates an error indicator based on the locator polynomial. The data correction system corrects each data bit error in the input data unit based on the error indicator.

Abstract: A method and apparatus for externally aided self adjusting real time clock have been disclosed. A circuit having a pulse train output is coupled to an adjusting circuit, a real-time clock is coupled to the adjusting circuit, and a proportional integral derivative time processor is coupled to the adjusting circuit, and where the adjusting circuit affects the pulse train output.

Abstract: A packet switch includes ingress ports, each of which contains a random access memory having a storage capacity for storing data. An ingress controller of the packet switch allocates the storage capacity of each random access memory among transaction types of packets by allocating credits to each of the transactions types for the random access memory. Each ingress port accepts packets based on the transaction types of the packets and the credits of the random access memory in the ingress port. Moreover, the ingress port stores accepted packets in the random access memory of the ingress port. In further embodiments, the ingress controller dynamically reallocates the credits of the random access memory in the ingress port during operation of the packet switch.

Abstract: A touch sensor is provided including a controller and a planar layout having an edge and an interior portion. Further including a connector coupling the touch controller to the layout; a substrate made of a first material; and sensing elements made of a second material formed on the substrate and covering the layout without overlapping. Sensing elements have non-monotonic widths from the center along two perpendicular directions, and a centroid. The touch sensor including pass-through traces to couple edge to interior portions to determine two-dimensional locations for touches using a weighting that is proportional to an overlap area of the sensor elements and their centroids. The substrate may be made of a dielectric and the sensing elements made of a conductor. A method for using a controller circuit having a memory to store centroid locations and determine a two-dimensional location on a touch screen as above is also provided.

Abstract: A computing system includes a codec device, a basic input-output system including both configuration data and feature data for the codec device, and a device driver for the codec device. The basic input-output system configures the codec device based on the configuration data. The device driver reads the feature data from the basic input-output system and enables one or more features of the codec device based on the feature data. In various embodiments, the device driver is WHQL certified and is included in an automated operating system upgrade of the computing system. Because the feature data is in the basic input-output system, the feature data is preserved during the operating system upgrade of the computing system. In some embodiments, the device driver enables one or more features of an application program based on the feature data.