Abstract: A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface that reads the delay code from the register and outputs the delay code to automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum chip speed.

Abstract: An integrated circuit includes a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal and a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal. The integrated circuit further includes a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input.

Abstract: Systems and methods are disclosed for performing data conversion by matching current sources using a thin oxide device; and minimizing voltage stress on the thin oxide device during operation or power down.

Abstract: A sensor is provided. The sensor includes a planar sensing area including a sensor layout. The sensor layout includes an interior portion, an edge portion, and edges. The sensor layout also includes interior sensing elements, the interior sensing elements being located in the interior portion, and edge sensing elements, the edge sensing elements being located in the edge portion. The interior sensing elements are arranged in the sensor layout such that the interior sensing elements generally do not extend beyond a predetermined distance from the edges. Moreover, the edge sensing elements are arranged to extend beyond the predetermined distance and interlace with the interior sensing elements in the interior portion. The sensor further includes a controller and a connector, the connector coupling the planar sensing area to the controller.

Abstract: Integrated circuit oscillators include a cascaded arrangement of first and second all-pass networks containing a resonator therein, such as a crystal-based resonator. The second all-pass network is configured to provide negative feedback to the first all-pass network at DC (i.e., very low frequencies) and is further configured to provide positive feedback with 90 degrees of phase to the first all-pass network at the resonant frequency of the resonator, which may be the third overtone frequency of a crystal resonator. The first all-pass network includes the resonator and the second all-pass network includes a resistor having resistance matched to a motional resistance of the resonator at the resonant frequency.

Abstract: A method and apparatus for an equalized On-Die Termination (ODT) circuit uses timed switching to reduce receiver power consumption.

Abstract: A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.

Abstract: A method and apparatus for implementation of PLL minimum frequency via voltage comparison have been described.

Abstract: A single replica current is proportional to current through a main switch of a switching power converter. This replica current may be used for current compensation, detection and response to an overload, detection and response to a super-overload, and combinations thereof. An input voltage is switchably coupled to an output signal generating a load current responsive to a switch control. A replica switch generates a replica current proportional to the load current. A ramp modulation signal may be generated. A voltage ramp of the ramp modulation signal may be adjusted in response to the replica current. A feedback difference signal is compared to the ramp modulation signal to generate a comparison output. Comparison of an overload reference voltage to a replica voltage proportional to the replica current generates an overload signal. The switch control is generated responsive to the comparison output and may be modified responsive to the overload signal.

Abstract: A multi-band clock generator includes a phase-locked loop (PLL) integrated circuit responding to first and second clock signals, and includes a multi-band voltage controlled oscillator (VCO) responding to a multi-bit control word that sets a frequency characteristic curve of the VCO. The multi-band clock generator also includes an adaptive frequency calibration (AFC) circuit responding to the first and second clock signals, and the AFC circuit is configured to look-up a first multi-bit control word during an operation to lock an output clock signal generated by the VCO to a first frequency characteristic curve associated with the first multi-bit control word.

Abstract: System and method for handshaking between first and second processors via a single wire connecting a first pin of the first processor and a second pin of the second processor are described. In one embodiment, the method comprises the first processor disabling an interrupt function on the first pin; and, subsequent to the disabling, interrupting the second processor by driving the first pin to a first logic level and then releasing the first pin to a second logic level.

Abstract: Methods of forming electro-micromechanical resonators provide passive temperature compensation of semiconductor device layers used therein. A first substrate is provided that includes a first electrically insulating temperature compensation layer on a first semiconductor device layer. A step is performed to bond the first electrically insulating temperature compensation layer to a second substrate containing the second electrically insulating temperature compensation layer therein, to thereby form a relatively thick temperature compensation layer. A piezoelectric layer is formed on the first electrically insulating temperature compensation layer and at least a first electrode is formed on the piezoelectric layer.

Abstract: A high-speed switch that includes a switch fabric, and both high-speed serial ports and data converter physical ports. A first set of data converter physical ports may perform analog-to-digital conversions, such that an external analog signal may be converted to a digital input signal on the switch. The converted digital input signal may then be routed through the switch fabric in accordance with a serial data protocol. A second set of data converter physical ports may perform digital-to-analog conversions, such that an internal digital signal received from the switch fabric may be converted to an analog output signal on the switch. The converted analog output signal may then be transmitted to an external destination in accordance with a serial data protocol.

Abstract: An integrated circuit chip implements a high-speed switch that includes: a switch fabric; control logic that controls the transmission of digital signals through the switch fabric; a transceiver block comprising one or more transceivers, each transmitting digital signals between the control logic and a corresponding external device; a data converter physical interface comprising one or more data converters, each performing a conversion between analog and digital signals, wherein digital signals associated with the one or more data converters are routed through the switch fabric; and a signal processing engine coupled to the control logic, wherein the signal processing engine performs on-chip processing of digital signals received from the transceiver block and the data converter physical interface.

Abstract: A communication system is disclosed. The communication system comprises a printed circuit board. The printed circuit board includes a plurality of channels; The communication system includes a plurality of receivers coupled to outputs of the plurality of channels; and a plurality of drivers coupled to inputs of the plurality of channels, wherein a slew rate for each of the plurality drivers is dependent on the transitions of its neighboring drivers. The communication system further includes a plurality of slew rate equalizers coupled to the plurality of drivers, wherein a slew rate driver coupled to a victim channel compensates for cross talk from its neighboring aggressor channels by adjusting its slew rate based upon a signal received from the slew rate equalizer of the victim channel.

Abstract: Method and apparatus for providing haptic feedback in connection with a capacitive sensing mechanism are described. In one embodiment, the apparatus comprises a convex, non-metallic structure arranged so as to maintain physical separation between an activator and the capacitive sensing mechanism until sufficient force is applied by the activator. The structure does not form a part of an electrical circuit comprising the capacitive sensing mechanism.

Abstract: A method of gain calibration of an ADC stage is provided. The method includes steps of receiving an input analog signal, converting the input analog signal into an m-bit digital signal by means of an analog to digital converter, generating a calibration signal by means of a random number generator, adding the calibration signal to the m-bit digital signal to produce an adjusted m-bit digital signal, converting the adjusted m-bit digital signal into an adjusted partial analog signal by means of a digital to analogue converter, subtracting the partial analog signal from the input analog signal, to produce a residual analog signal, amplifying the residual analog signal. The the calibration signal may take any one of three values and may be constrained to one of only two of these three values. An ADC stage adapted to operate according to the method is also provided.

Abstract: Public scheduling tables of PCI-Express network devices are remapped into private scheduling tables having different data structures. The private scheduling tables enable the construction of parallel-processing selection engines (ones with look-ahead selection capabilities) that are more compact in size than would have been possible with use of the data structures of the public scheduling tables. In one embodiment, residual weight values are re-shuffled so as to move each winner of an arbitration round away from a winner's proximity bar by a distance corresponding to an initial weight assigned to the winner. The initial weight can be proportional to the reciprocal of a bandwidth allocation assigned to each data source.

Abstract: Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.

Abstract: A circuit for an N-bit stage (110i) of a pipeline ADC having L=2N levels, the circuit comprising: an operational amplifier (420); a first feedback capacitor (Cf1) having a first plate connected to an input of the operational amplifier and a second plate switchably connected on a first clock signal (?1) to a first input voltage (±Vm) and on a second clock signal (?2) to an output of the operational amplifier; a second feedback capacitor (Cf2) having a first plate connected to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a discharge connection and on the second clock signal (?2) to an output of the operational amplifier; and a plurality of K sampling capacitors (Cu), each sampling capacitor having a first plate connected on the first clock signal to the input of the operational amplifier and a second plate switchably connected on the first clock signal to a second input voltage (Vin) and on the second clock signal to one of a positive and negative r