Patents Assigned to Integrated Device Technology
  • Patent number: 8312190
    Abstract: A serial buffer includes a first port configured to operate in accordance with a first serial protocol and a second port configured to operate in accordance with a second serial protocol. A first translation circuit of the serial buffer allows packets received on the first port to be translated to the second serial protocol, and then transferred to the second port. A second translation circuit of the serial buffer allows packets received on the second port to be translated to the first serial protocol, and then transferred to the first port. Translations may be performed in response to information included in the headers of the received packets, including source ID values, destination ID values and/or case number values.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: November 13, 2012
    Assignee: Integrated Device Technology, inc.
    Inventors: Chi-Lie Wang, Jason Z. Mo
  • Patent number: 8295293
    Abstract: A packet switch issues credits to a link partner based on credit values and updates the credit values to indicate credits consumed by the link partner based on packets received from the link partner by the ingress port. Additionally, the packet switch selects credit threshold values corresponding to a transmission period of imminent credit starvation of the link partner and compares the updated credit values with the credit threshold values. The packet switch issues additional credits to the link partner when at least one of the updated credit values has reached a corresponding credit threshold value. In some embodiments, the packet switch also issues additional credits to the link partner during idle transmission periods.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: October 23, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventor: David Alan Brown
  • Patent number: 8294249
    Abstract: A lead frame package is disclosed where transmission signals are coupled into a die from a pair of lead frames through bonding wires that are separated by no more than three times a diameter of one of the bonding wires. In some embodiments, pairs of lead frames carrying differential transmission signals can be shielded by adjacent pairs of ground and power leads that are coupled into the die through bonding wires that are also separated by no more than three times a diameter of one of the bonding wires.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: October 23, 2012
    Assignee: Integrated Device Technology Inc.
    Inventors: David J. Pilling, Jitesh Shah, Diane Peng, Derek Huang
  • Patent number: 8289061
    Abstract: A method is provided for improving clock recovery signal jitter in digital communication based on a phase adjustment technique in a phase interpolation. A clock signal is expressed as the combination of two sinusoidal signals. The phase interpolating process determines the amplitude of the first sinusoidal signal, and the amplitude of the second sinusoidal signal that is 90° out of phase from the first sinusoidal signal. The clock signal is then formed by combining first sinusoidal signal with the second sinusoidal signal by choosing the first and second amplitude such that the amplitude of the clock signal is substantially a constant. Modulation of the clock signal amplitude is significantly improved by the disclosed technique over the conventional technique when the sum of the first and second amplitudes of the two sinusoidal functions is kept a constant.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: October 16, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Hui Wang, Lixin Jiang
  • Patent number: 8289989
    Abstract: A packet switch includes an arbiter that generates an availability signal indicating whether one or more pseudo-ports are available for receiving data. Each pseudo-port identifies one or more output ports of the packet switch. An input port of the packet switch receives data of a data packet, generates a grant request identifying a pseudo-port, and issues the grant request to a grant request filter. The grant request filter determines based on the availability signal whether the grant request is serviceable by the packet switch. If the grant request is a serviceable grant request, the grant request filter issues the grant request to the arbiter. The arbiter can select the serviceable grant request and issue a grant to the input port. The data of the data packet can then be routed from the input port to each output port identified by the pseudo-port.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: October 16, 2012
    Assignee: Integrated Device Technology Inc.
    Inventor: David Gibson
  • Patent number: 8284091
    Abstract: An analog-to-digital converter comprises a signal input (6) for receiving an analog input signal and a set of comparators (4). Each comparator (4) has a first input (21) connected to the signal input (6) and a second input (22) connected to a reference voltage (16). Each comparator generates an output based on the comparison of the signals at the first input (21) and second input (22). The reference voltage is the same for all comparators. The set of comparators (4) has a non-identical response to the reference voltage (16) and the input signal and is due to an internally arising offset. An adder (25) determines a sum of the outputs of the set of comparators and conversion logic (27) generates an output digital signal dependent on the determined sum. Multiple sets of comparators can be provided, each set having a different respective reference voltage.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: October 9, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Hendrik Van Der Ploeg, Erwin Janssen, Konstantinos Doris
  • Patent number: 8285884
    Abstract: A deskew module of a receiver includes deskew units, each of which includes a data aggregation module for selecting a data rate for receiving symbols of a corresponding data stream. The deskew unit includes a data aggregation module that aggregates a predetermined number of the symbols in one or more clock cycles of a clock signal based on the data rate. The predetermined number of symbols is the same for each data rate selectable by the data aggregation module. The data aggregation module outputs the aggregated symbols to a deskew buffer of the deskew unit in a clock cycle of a clock signal. The deskew buffer deskews symbols received from the data aggregation module and outputs the deskewed symbols.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: October 9, 2012
    Assignee: Integrated Device Technology Inc.
    Inventor: Christopher I. W. Norrie
  • Patent number: 8283256
    Abstract: Methods of forming substrates having two-sided microstructures therein include selectively etching a first surface of the substrate to define a plurality of alignment keys therein that extend through the substrate to a second surface thereof. A direct photolithographic alignment step is then performed on a second surface of the substrate by aligning a photolithography mask to the plurality of alignment keys at the second surface. This direct alignment step is performed during steps to photolithographically define patterns in the second surface.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: October 9, 2012
    Assignee: Integrated Device Technology inc.
    Inventors: Wanling Pan, Harmeet Bhugra
  • Patent number: 8284816
    Abstract: A spread spectrum clock signal generator modulates a reference clock signal based on a spread spectrum frequency profile and includes a phase-lock loop for generating a spread spectrum clock signal by aligning a phase of the modulated reference clock signal with a phase of the spread spectrum clock signal. The spread spectrum clock signal generator also includes a loop modulator for modulating the spread spectrum clock signal based on the spread spectrum frequency profile. Because the spread spectrum clock signal generator modulates both the reference clock signal and the spread spectrum clock signal based on the spread spectrum frequency profile, the spread spectrum clock signal has a non-distorted frequency profile and low phase jitter.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: October 9, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventor: Daniel M. Clementi
  • Patent number: 8284790
    Abstract: A packet switch receives packets at an ingress port, generates enqueue records for the packets, and stores the enqueue records in an enqueue structure. The enqueue record of a packet includes a pass flag for indicating whether a permissive passing rule is applicable to the packet. The packet switch determines a routing order for the packets stored in the ingress port based on the enqueue records and a set of ordering rules including the permissive passing rule. If a packet is blocked in the packet switch, the packet switch identifies an oldest unblocked routable packet stored in the ingress port based on the enqueue records and the set of ordering rules. Further, the packet switch routes the oldest unblocked routable packet through the packet switch. In this way, the packet switch allows the oldest unblocked routable packet to pass the blocked packet in the packet switch.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: October 9, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Raghunath Reddy Kommidi, David Alan Brown
  • Patent number: 8279007
    Abstract: A switch circuit is provided. The switch circuit may include a first transistor having a source terminal to accept an input signal, a drain terminal to provide an output signal, and a gate; a power supply providing a gate voltage. The switch circuit may also include a circuit to couple a switch signal to the gate, wherein the circuit turns the first transistor ‘off’ for all values of the input signal when the switch signal is ‘low.’ A programmable gain amplifier (PGA) is also provided. The PGA may include an input stage having an input node to couple an input signal, and an output node to provide a gate signal, at least a first gain stage including a resistor and a switch circuit as above. A differential gain amplifier may be included to provide an output signal from the gain signal.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: October 2, 2012
    Assignee: Integrated Device Technology, inc.
    Inventors: ChangMing Wei, Yu Zhang, Lixin Jiang, JinFu Chen, Jeffrey G. Barrow
  • Publication number: 20120242309
    Abstract: A controlled headroom low dropout regulator (CHLDO) having an LDO with an input voltage provided by a capacitor. An incremental voltage is added to an output voltage of the LDO to create a reference voltage. The reference voltage is compared to the input voltage to determine when to couple/de-couple the capacitor with a current source. If the capacitor is coupled to the current source, the capacitor will charge only if the voltage driven by the current source exceeds the input voltage provided by the capacitor. When the input voltage developed on the capacitor exceeds the reference voltage, the capacitor is automatically de-coupled from the current source. Multiple CHLDOs can be charged from a single current source, wherein charging automatically proceeds from the lowest voltage CHLDO to the highest voltage CHLDO.
    Type: Application
    Filed: March 22, 2011
    Publication date: September 27, 2012
    Applicant: Integrated Device Technology, Inc.
    Inventor: Kenneth A. Korzeniowski
  • Patent number: 8265219
    Abstract: A method and apparatus for fast PLL initialization have been disclosed where control of a VCO is based on a selected control signal which is based upon either a comparison signal or a prespecified signal.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 11, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventor: Stanley Hronik
  • Publication number: 20120223647
    Abstract: Energy sharing circuits and related methods are disclosed herein. A high voltage can be selectively coupled to a first source line and a low voltage can be selectively coupled to a second source line during a first time period. During a subsequent time period, a first coupling switch is activated to inductively couple the first source line to the second source line and diode block the second source line from the first source line. During a subsequent time period, the low voltage is selectively coupled to the first source line and the high voltage is selectively coupled to the second source line. During a subsequent time period, a second coupling switch is activated to inductively couple the second source line to the first source line and diode block the first source line from the second source line.
    Type: Application
    Filed: March 3, 2011
    Publication date: September 6, 2012
    Applicant: Integrated Device Technology, Inc.
    Inventors: A. Paul Brokaw, June Her, Jeffrey G. Barrow
  • Patent number: 8259888
    Abstract: The present invention provides a method of processing signal data comprising generating a first clock signal and a second clock signal and processing the signal data using the first clock signal and the second clock signal. While processing the signal data, the phase difference between the first clock signal and the second clock signal is measured and corrected for so that a target phase difference between the first clock signal and the second clock signal is maintained.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: September 4, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Junqi Hua, Alberto Baldisserotto, Steven White
  • Patent number: 8254399
    Abstract: A method and apparatus for adaptive buffer management for traffic optimization on switches have been disclosed where pattern injection and traffic monitoring with forced congestion allows optimizing buffers while accounting for actual system delays.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: August 28, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chi-Lie Wang, Jason Z Mo
  • Patent number: 8254515
    Abstract: A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator; determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: August 28, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Dongming Lou, Pengfei Hu, Junqiang Shang, Xin Liu
  • Patent number: 8255599
    Abstract: In PCI-Express and alike communications systems, data bandwidth per channel can vary as a result of negotiated port bifurcation during network bring-up. Disclosed are systems and methods for adjusting FIFO depths in response to negotiated bandwidth per channel so that data absorbing FIFO's of respective channels are not arbitrarily too deep or too shallow relative to the data bandwidths of the channels the FIFO's serve.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: August 28, 2012
    Assignee: Integrated Device Technology inc.
    Inventor: Nadim Shaikli
  • Patent number: 8248135
    Abstract: A circuit (10) includes a circuit input (12), a circuit output (16) and a one or more delay elements (22) positioned between the circuit input (12) and the circuit output (16). The delay elements (22) each include a differential input pair (234), a latch stage (236) and a delay controller (244A1, 244A2, 244B1, 244B2). The delay controller (244A1, 244A2, 244B1, 244B2) selectively apportions current between the differential input pair (234) and the latch stage (236) to achieve a desired delay value for the circuit (10). The circuit (10) can also include a feedback loop (18) that calibrates a DC offset of the delay elements (22). The delay elements (22) can include two or more sets of resistive loads (238A, 238B) and a rate controller (241). The rate controller (241) controls an on/off state of the resistive loads (238A, 238B) to selectively switch between full resistance and half resistance.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: August 21, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Yue Yu, Han Bi
  • Patent number: 8248383
    Abstract: A touch screen includes a plurality of single-layer ITO bars having a substantially rectangular shape and arranged in parallel to each other in order to detect touches on the touch screen. The location of a touch on the touch screen in the direction along an ITO bar is determined by applying a signal on one end of the ITO bar and measuring the change in the amplitude and the delay of the signal on the opposite end of the ITO bar. Such application and measurement of the signal can be repeated with the application of the signal occurring on the opposite end of the ITO bar and the measurement of the signal occurring on said one end of the ITO bar, in order to enhance the accuracy of the measurement.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: August 21, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Christopher William Dews, Charles Henry Seaborg, Jr.