Abstract: Level shifting circuits and related methods are disclosed herein. The level shifting circuit includes a cross-coupled pull-up circuit coupled to a higher supply voltage, an output signal, and an inverted output signal. An input signal transitions between a ground and a lower supply voltage and an inverted input signal transitions in a direction opposite from the input signal between the ground and the lower supply voltage. A first n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the output signal, and a source coupled to the inverted input signal. A second n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the inverted output signal, and a source coupled to the input signal. The level shifting circuit may be included in an IC with core logic in a first voltage domain and input/output logic in a second voltage domain.

Abstract: A high voltage tolerant transceiver operating at a low voltage is provided, including two input/output pads to receive a receive signal and transmit a transmit signal; a transmitter block to transmit the transmit signal; a receiver block to receive the receive signal and provide an amplified signal; at least one of the transmitter block and the receiver block further comprising at least two NMOS transistors having their gate coupled to a low power supply to receive the low voltage, their substrate coupled to ground, and their source coupled to the input/output pad. Also provided is a circuit to isolate the output of a transmitter from high voltages, including a first transistor and a second transistor. Also provided is a substrate isolating circuit, including a first transistor, a second transistor, and a third transistor so that the substrate voltage is isolated from a high voltage in the pads.

Abstract: A voltage-mode line driving circuit is provided. The voltage-mode line driving circuit includes a driving circuit, the driving circuit receiving, as an input signal, a feedback signal, and outputting an output signal. The voltage-mode line driving signal also includes an adaptive tuning circuit coupled to the driving circuit, the adaptive tuning circuit receiving as input signals the feedback signal and the output signal and adaptively outputting a modifying signal to the driving circuit which modifies the feedback signal.

Abstract: Successive approximation Analog-to-digital converters (ADCs) and related methods are disclosed. A successive approximation ADC includes a comparator with a comparator output and inputs coupled to a common model signal and a compare input. Control logic generates one or more control signals responsive to the comparator output. A capacitor array includes first sides of capacitors operably coupled to an array output. The capacitor arrays selectively couples each of second sides of the capacitors to an analog input signal and one or more input reference signals responsive to the one or more control signals. A voltage limiter is operably coupled between the array output and the compare input of the comparator and limits a voltage on the compare input to within a predefined range relative to the array output. The successive approximation ADC may also be configured differentially with a second comparator and a second voltage limiter.

Abstract: A data receiver identifies an alignment symbol in a parallel data stream including encoded symbols, generates a bit order indicator indicating a bit order of the alignment symbol identified in the parallel data stream, and generates a symbol stream including the encoded symbols. Further, the data receiver decodes symbols in the symbol stream and generates a bit polarity indicator indicating a bit polarity of the parallel data stream based on the decoded symbols. Additionally, the data receiver generates a formatted symbol stream having a predetermined bit order and a predetermined bit polarity, based on the symbol stream, the bit order indicator, and the bit polarity indicator. In some embodiments, the data receives a serial data stream and generates the parallel data stream by deserializing data in the serial data stream.

Abstract: Microelectromechanical resonators include a resonator body anchored to a surrounding substrate by at least one support that holds the resonator body opposite a recess in the substrate. The resonator body has first and second pluralities of interdigitated drive and sense electrodes thereon. The first plurality of interdigitated drive and second electrodes are aligned to a first axis of acoustic wave propagation in the resonator body when the resonator body is operating at resonance. In contrast, the second plurality of interdigitated drive and sense electrodes are aligned to a second axis of acoustic wave propagation in the resonator body. This second axis of acoustic wave propagation preferably extends at an angle in a range from 60° to 120° relative to the first axis and, more preferably, at an angle of 90° relative to the first axis.

Abstract: A calibration system employed for use with a resistance capacitance (RC) filter having resistors and capacitors with parasitic capacitance associated therewith. The calibration system has a digital calibration circuit receiving a time constant signal and generating, based thereon, a control word of N digital bits. The calibration system includes an analog monitor circuit having monitor capacitance assembly having a particular equivalent resistor and capacitor configuration. The analog monitor circuit generates the time constant signal and includes N switches, where each switch is controlled by one of the N bits of the control word, each switch is configured to connect or disconnect one or more capacitors of the monitor capacitor assembly thereby generating a time constant signal that represents the time constant of the RC integrated filter.

Abstract: A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (IS) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.

Abstract: Analog to digital conversion is performed by sampling an input voltage followed by AD conversion of the sampled voltage. In the sample and hold circuit a differential amplifier output voltage is generated between the first and second output of a differential amplifier in response to the sampled input voltage. A conversion polarity is selected by connecting the one output or the other of the differential amplifier to a circuit node in an AD conversion circuit using a first or second switch. These switches from both outputs of the differential amplifier to the same circuit node of the AD conversion circuit are both made conductive simultaneously prior to making the selected one of the first and second switch conductive. In this way, the amplifier output voltage is reset without requiring a dedicated switch just for this purpose.

Abstract: A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses baseband signal samples resulting from analog to digital conversion of a received analog signal followed by digital downconversion. The compressed signal samples are transferred over the serial data link to the baseband processor then decompressed prior to normal signal processing. For the downlink, the baseband processor compresses baseband signal samples and transfers the compressed signal samples to the RF unit. The RF unit decompresses the compressed samples prior to digital upconversion and digital to analog conversion to form an analog signal for transmission over an antenna. Compression and decompression can be incorporated into operations of conventional base stations and distributed antenna systems, including OBSAI or CPRI compliant systems.

Abstract: A method and apparatus for duty-cycle correction with reduced current consumption have been described.

Abstract: A syndrome generator generates odd syndromes of a sequence of syndromes and stores the odd syndromes in registers. A syndrome sequencer identifies the register storing the next syndrome of the sequence of syndromes, reads the syndrome from the register, and outputs the syndrome to a sequential polynomial generator. Further, the syndrome sequencer generates an even syndrome by squaring the syndrome read from the register and writes the even syndrome into the same register. Moreover, the syndrome sequencer outputs each syndrome of the sequence of syndromes in sequential order. The sequential polynomial generator generates a locator polynomial in a number of iterations based on the sequence of syndromes received from the syndrome sequencer.

Abstract: A method and apparatus for dynamic traffic management with packet classification have been disclosed where packet size, variation, and count may be used to select credit or packet based arbitration.

Abstract: A method and apparatus for A Low Power AC On-Die-Termination (ODT) Circuit using active components reduces receiver power consumption.

Abstract: A method and apparatus for an equalized On-Die Termination (ODT) circuit uses timed switching to reduce receiver power consumption.

Abstract: Level shifting circuits and a related method are disclosed herein. An embodiment of the present invention includes a voltage level shifter, comprising a first pull up transistor coupled to a high voltage signal and a first pull down transistor coupled between the first pull up transistor and a low voltage signal and controlled by an input signal. The voltage level shifter further includes a first bias transistor serially coupled between the first pull up transistor and the first bias transistor. A gate of the first bias transistor is coupled with a bias voltage signal. The voltage level shifter further includes a first additional pull up path coupled with the high voltage signal and a first node between the first pull up transistor and the first pull down transistor, and an output signal associated with the first node. The output signal is a level shifted voltage responsive to the input signal.

Abstract: A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses baseband signal samples resulting from analog to digital conversion of a received analog signal followed by digital downconversion. The compressed signal samples are transferred over the serial data link to the baseband processor then decompressed prior to normal signal processing. For the downlink, the baseband processor compresses baseband signal samples and transfers the compressed signal samples to the RF unit. The RF unit decompresses the compressed samples prior to digital upconversion and digital to analog conversion to form an analog signal for transmission over an antenna. Compression and decompression can be incorporated into operations of conventional base stations and distributed antenna systems, including OBSAI or CPRI compliant systems.

Abstract: A method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches have been disclosed where a buffer availability is based on a programmable reservation size for dynamic allocation.

Abstract: A method and apparatus for fail-safe start-up circuit for subthreshold current sources have been disclosed.

Abstract: A serial buffer includes a first port configured to operate in accordance with a first serial protocol and a second port configured to operate in accordance with a second serial protocol. A first translation circuit of the serial buffer allows packets received on the first port to be translated to the second serial protocol, and then transferred to the second port. A second translation circuit of the serial buffer allows packets received on the second port to be translated to the first serial protocol, and then transferred to the first port. Translations may be performed in response to information included in the headers of the received packets, including source ID values, destination ID values and/or case number values.