Abstract: A divider can include a phase selection circuit that switches between a plurality of phase-separated clock signals in response to a fractional control signal to form a selected clock signal, the selected clock signal being utilized to generate a second clock signal; and a counter that receives the second clock signal and generates the fractional control signal and a transition control signal, the transition control signal indicating when the second clock signal should switch states in response to a transition of the selected clock signal, the counter generating a feed-back clock signal.

Abstract: Exemplary embodiments of the invention provide a clock generation apparatus, system, and method, which include power management. The apparatus is couplable to second circuitry which has a clock input terminal and an inverted clock output terminal. An exemplary apparatus comprises a clock generator, a sensor, and a processor. The clock generator provides a clock signal on a first terminal which is couplable to the clock input terminal of the second circuitry. The sensor is coupled to a second terminal which is couplable to the inverted clock output terminal, and detects a power conservation mode and a power resumption mode of the second circuitry. The processor is adapted to reduce power to the clock generator and to provide a first predetermined voltage or a second predetermined voltage to the first and second terminals in response to the detection of the power conservation mode, and to increase power to the clock generator in response to the detection of the power resumption mode.

Abstract: Level shifting circuits and a related method are disclosed herein. An embodiment of the present invention includes a voltage level shifter, comprising a first pull up transistor coupled to a high voltage signal and a first pull down transistor coupled between the first pull up transistor and a low voltage signal and controlled by an input signal. The voltage level shifter further includes a first bias transistor serially coupled between the first pull up transistor and the first bias transistor. A gate of the first bias transistor is coupled with a bias voltage signal. The voltage level shifter further includes a first additional pull up path coupled with the high voltage signal and a first node between the first pull up transistor and the first pull down transistor, and an output signal associated with the first node. The output signal is a level shifted voltage responsive to the input signal.

Abstract: A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory block including an array of memory cells; an address decoder coupled to each of the at least one memory block, the address decoder including a comparator coupled to receive an input address and a block address and provide a compare bit that indicates when a portion of the input address matches the block address, and an OR gate coupled to receive the compare bit and a wildcard bit, the OR gate providing an enable to the memory block when either the compare bit or the wildcard bit is asserted; and a logic unit that receives a mode value and the input address and provides the wildcard bit to each of the address decoders. Data can be simultaneously written into the memory array in patterns in accordance with the mode value.

Abstract: A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency.

Abstract: An analog-to-digital converter with comparators with multiple, inter-coupled, outputs is provided, which may be also called a Benorion Analog-to-Digital Converter (ADC) or a Benorion Converter. The analog-to-digital converter includes a plurality of comparators operably coupled for receiving an analog input signal and configured for comparing the analog input signal with a plurality of voltage reference signals. Each comparator of the plurality is configured for generating a plurality of comparator outputs comprising a primary comparator output, and at least one additional comparator output selected from the group consisting of positive comparator outputs and negative comparator.

Abstract: A packet switch includes virtual output queues for mapping data units of data packets from input ports to output ports of the packet switch. The packet switch selects virtual output queues based on old age indicators of the virtual output queues and routes data units mapped at heads of the selected virtual output queues to output ports of the packet switch. Further, the packet switch may identify a data unit of a multicast data packet mapped at the head of more than one virtual output queue and contemporaneously route the data unit to more than one output port. Additionally, the packet switch may update an old age indicator to indicate a virtual output queue is old if the virtual output queue maps an unserviceable data unit of a multicast data packet and the same data unit is mapped at the head of a selected virtual output queue.

Abstract: An equalization system (18) that reduces inter-symbol interference in an input signal (220) includes a variable gain amplifier (430), and one or more peaking amplifiers (432) that are connected in series to the variable gain amplifier (430). The variable gain amplifier (430) receives the input signal (220) and scales the input signal (220) while each peaking amplifier (432) can be selectively controlled to selectively adjust a peaking gain (326) and a peaking corner frequency (328). Additionally, the equalization system (18) can include a PTAT bias generator (434) that provides a PTAT bias current to one or more of the peaking amplifiers (432) to maintain a transconductance of one or more of the peaking amplifiers (432) substantially constant as temperature changes. With this design, the equalization system (18) provides programmable and stabilized equalization gain, has a tunable peaking corner frequency, and superior common mode rejection.

Abstract: N-channel field effect transistor Proportional To Absolute Temperature (N-PTAT) cells are connected to a first supply voltage and P-channel field effect transistor Proportional To Absolute Temperature (P-PTAT) cells are connected to a second supply voltage. A coupling circuit connects at least one of the N-PTAT cells to at least one of the P-PTAT cells. These circuits can be used to provide a voltage reference and/or a supply voltage level detector. Related operating methods are also described.

Abstract: A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training sequence header pattern. Based on each of the first data frames, the plurality of serial lane transceivers de-skew a plurality of data frames and generate a plurality of event signals. Using the plurality of event signals, a core clock, having a first phase, is adjusted to be phase aligned with the slowest bit lane.

Abstract: A method and a corresponding system for characterizing the performance of a clock and data recovery circuit in a digital transceiver is presented. The method comprises phase modulating a jitter-free data signal by a testing signal having added data jitter and measuring the time the clock and data recovery system takes to achieve bit lock of a phase modulated signal. Data uncorrelated timing jitter corresponding to a user defined probability distribution is included in the jitter testing signal. Utilization of a variable probability distribution in generating data uncorrelated timing jitter, as provided by the present invention, allows for greater flexibility and accuracy in clock and data recovery circuit testing and characterization.

Abstract: An error correction code system includes an error correction code generator for generating an error correction code based on a data unit and an error detector for detecting at least one bit error in the data unit based on the error correction code. The error correction code generator includes logic circuits for generating check bits in the error correction code. The error detector includes logic circuits for identifying any data bits of the data unit having a bit error based on the error correction code. The logic circuits in the error correction code generator and the error detector are derived from group codes separated from each other by a hamming distance and having a same population count. The error correction code system may also include an error corrector for correcting error bits in the data unit.

Abstract: A method and apparatus for queue concatenation have been disclosed.

Abstract: A phase interpolator is provided. The phase interpolator comprises a plurality of reference stages, the reference stages receiving a reference signal having a predetermined phase and outputting a component signal, wherein the reference stages comprise a plurality of current source circuits, and the current source circuits comprise a plurality of transistors, and the transistors of the current source circuits are coupled to one another by the drains of the transistors.

Abstract: A packet switch includes individual route tables for ports of the packet switch. Each route table is associated with a port and individually maps a destination identifier of a data packet received at the port to another port in the packet switch. In some embodiments, the packet switch routes a data packet to an intermediate device based on a destination identifier in the data packet. The intermediate device services the data packet and sends the data packet, which includes the same destination identifier, back to the packet switch. In turn, the packet switch routes the data packet to a destination device based on the destination identifier in the data packet. The destination device terminates the data packet and may further service the data packet. In this way, the packet switch routes the data packet to both the intermediate device and the destination device based on the same destination identifier.

Abstract: A method and apparatus for packet cut-though have been disclosed. In packet cut-through mode successive packet fragments are associated an identical logical data flow. This allows, for example, a SPI-4 interface to be able to successively transmit a whole packet for a logical port without intervening by traffic of other logical ports.

Abstract: A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is developed on the MSB node. A compensation capacitor coupled to the MSB node has a compensation capacitance selected to offset the jump error voltage introduced by the parasitic capacitance. The compensation capacitor is enabled when all of the LSB capacitors are coupled to digital input signals having a logic ‘0’ state. Otherwise, the compensation capacitor is disabled (e.g., left in a floating state).

Abstract: A method and apparatus are disclosed for predicting the failure of a functional element of an integrated circuit during operation. The method includes determining whether the functional element of the integrated circuit device is in an idle cycle, elevating the temperature of the functional element above a normal operating temperature, performing a stress test of the functional element while the functional element is in the idle cycle, and indicating that the functional element, if it fails the stress test, is a potential future failing element. The stress test can include simultaneously providing a margining test voltage and a stress clock signal to the functional element while the temperature is elevated or at a normal operating temperature. The stress test is performed in the background, during continuous operation of the integrated circuit device, such that normal operation of the integrated circuit device is not interrupted.

Abstract: An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal.

Abstract: A biphase mark signal receiver includes a data and clock recovery circuit. The data recovery circuit may include a coarse recovery stage and a fine recovery stage. The coarse recovery stage is configured to detect repeating occurrences of a first preamble (e.g., Y-preamble) within a biphase encoded data stream received by the data recovery circuit. The fine recovery stage is configured to generate a recovered data stream, in response to estimating a plurality of timing decision points (e.g., 3UI, 2UI and 1UI) from the repeating occurrences of the first preamble detected by the coarse recovery stage.