Abstract: A clock circuit includes a phase-lock loop and a holdover circuit. The phase-lock loop generates an output clock signal having a constant frequency based on a loop filter voltage of a loop filter in the phase-lock loop. The holdover circuit generates and stores a digital value indicating the loop filter voltage and generates an analog voltage signal having the loop filter voltage indicated by the digital value. Further, the holdover circuit maintains the output clock signal at the constant frequency during a holdover of the phase-lock loop by regenerating the loop filter voltage based on the analog voltage signal. Because the analog voltage signal is based on the digital value, the voltage of the loop filter does not decay over time during the holdover of the phase-lock loop. As a result, the output clock signal remains at the constant frequency during the holdover of the phase-lock loop.

Abstract: A packet switch including input ports having various input bandwidths initializes credit values for the input ports. An arbiter of the packet switch selects input ports based on the credit values and routes data packets from the selected input ports to a switch fabric of the packet switch. The switch fabric routes data packets from the selected input ports to output ports of the packet switch. Moreover, the arbiter modifies the credit value of each selected input port based on the latency for routing the data packet from the selected input port to the switch fabric. In this way, the arbiter promotes fairness in routing additional data packets through the packet switch. In some embodiments, the switch fabric includes a buffered crossbar and the arbiter modifies credit values of crosspoints in the buffered crossbar based on the latency for routing data packets from the crosspoints to the output ports.

Abstract: A high voltage switch having first and second states includes an input receiving an input voltage that is greater than a supply voltage. Each of first, second, and third MOS structures of a first conductivity type has a gate, a source, and a drain. The sources and drains of each of the MOS structures are electrically coupled in series between the input and ground. An output is electrically coupled to the input. When the switch is in the first state, the gate of the first MOS structure is pulled to ground, the gate of the second MOS structure is pulled to the supply voltage, and the gate of the third MOS structure is pulled to a voltage greater than the supply voltage and less than the input voltage. When the switch is in the second state, the gates of all of the MOS structures are pulled to the supply voltage.

Abstract: A method and apparatus for generating a spread spectrum reference clock is presented. A method and apparatus is presented for receiving a spread spectrum parameter from a phase lock loop, wherein the spread spectrum parameter includes a multiple-level parameter comprising a plurality of phase signals; quantizing a spread spectrum profile associated with the spread spectrum parameter; mapping the quantized profile; generating control signals based on the mapping, wherein the control signals include an integer control signal and a phase control signal; dividing a phase signal of the plurality of phase signals with the integer control signal; synchronizing the divided phase signal using the phase control signal; and providing a reference clock for a spread spectrum clock generator based on the synchronizing.

Abstract: A method and apparatus for ground bounce and power supply bounce detection in devices have been disclosed. In one case one input to a differential amplifier is coupled to a reference voltage and another input to the differential amplifier is coupled to a measurement point and the output of the differential amplifier is coupled to a flip flop. The flip flop has an output indicating when a bounce threshold is exceeded.

Abstract: A level-shifting circuit with reduced shoot-through current includes an output circuit comprising high-voltage devices with a pull-up circuit configured for pulling up a voltage on an output signal to a high voltage responsive to a high-side control signal. The output circuit may also include a pull-down circuit configured for pulling down the voltage on the output signal to a low voltage in responsive to a low-side control signal. The level-shifting circuit can also include a high-side inverting buffer operably coupled between an edge-controlled signal and the high-side control signal, and a low-side buffer configured for driving the low-side control signal responsive to an input signal. The level-shifting circuit may also include an edge-control buffer operably coupled between the input signal and the high-side inverting buffer and configured to generate the edge-controlled signal with a slow rise time relative to a fall time.

Abstract: A boost regulator system for regulating one or more output voltages includes, a first pump element coupled to receive a first input voltage, a first switching device coupled to the first pump element, the first switching device causing a finite amount of energy to be stored in the first pump element in response to a first control signal. The system further includes, a first capacitor coupled to the first pump element and the first switching device, the first capacitor storing the finite amount of energy and generating a first output voltage in response to the finite amount of energy. A boost controller (BC) coupled to receive the first output voltage, the boost controller further configured to regulate the first output voltage by generating the first control signal.

Abstract: A novel method and system for clock and data recovery in high speed serial transceiver applications allowing for fast bit lock acquisition and small data tracking error is presented. The clock and data recovery method utilizes a variable bandwidth loop filter to generate a phase adjustment signal used by a phase interpolator in generating a clock signal at the same frequency and phase as the incoming digital data stream. The loop filter bandwidth may be adjusted to correspond with a plurality of clock and data recovery operating modes. In particular, the filter bandwidth may be set to either a high or a low value depending on whether the phase difference between the recovered clock signal and the incoming digital data stream is above or below a programmed threshold value.

Abstract: A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a data buffer for each data stream that stores a minimal skip ordered set based on the skip ordered set in the data stream received by the data buffer. Each of the minimal skip ordered sets has a same number of symbols. Additionally, each buffer stores data of the data stream received by the data buffer. The receiver aligns the data among the data buffers based on the minimal skip ordered sets in the data buffers and outputs the aligned data. In this way, the receiver deskews the data in the data streams.

Abstract: Automated clock relationship detection may quickly and reliably detect a clock relationship with minimal latency while reducing problems due to metastability occurring at a solitary instant or extended over multiple clock periods. Automated clock relationship detection between two clocks may comprise (a) a shift register synchronizer that reduces the possibility of metastability while capturing and temporarily storing samples of the first clock in response to cycles of the second clock and (b) an evaluator that processes the samples to determine the relationship. A clock relationship detector may also determine the relationship of two clocks by arbitrating a plurality of preliminary determinations of the relationship. Delays may be applied so that each of several detectors receives a clock at a different time, which may avoid metastability in the majority of detectors. The relationship may be used to reliably determine an operating mode of logic driven by one of the clocks.

Abstract: A load circuit for a crystal oscillator includes a plurality of capacitors and a load control circuit configured to selectively add the capacitors to a load at a terminal of the crystal oscillator responsive to a command signal to provide a non-linear capacitive load at the terminal of the crystal oscillator that compensates for a non-linearity of a frequency versus load capacitance characteristic of the crystal oscillator. The load circuit may include a plurality of switches, respective ones of which are configured to load a terminal of the crystal oscillator with respective ones of the capacitors, and control circuit configured to control the plurality of switches to load the terminal of the crystal oscillator responsive to a binary command signal such that respective single ones of the switches operates in response to respective quantum changes a binary command signal over an operating range of the binary command signal.

Abstract: A method and apparatus for varying an output clock signal frequency to match the frequency of an output data signal frequency for a SERDES circuit while maintaining a constant input clock frequency is shown. According to this method and apparatus, a PMA rate signal may control the frequency of the output clock while a datastrobe signal may be used to control the frequency of the data signal. Accordingly, the apparatus and methods may be used to produce an output data signal and a clock signal having frequencies that may be lower than the frequency of the input clock signal.

Abstract: An integrated circuit chip implements a high-speed switch that includes: a switch fabric; control logic that controls the transmission of digital signals through the switch fabric; a transceiver block comprising one or more transceivers, each transmitting digital signals between the control logic and a corresponding external device; a data converter physical interface comprising one or more data converters, each performing a conversion between analog and digital signals, wherein digital signals associated with the one or more data converters are routed through the switch fabric; and a signal processing engine coupled to the control logic, wherein the signal processing engine performs on-chip processing of digital signals received from the transceiver block and the data converter physical interface.

Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference, with multiple operating modes, such power conservation, clock, reference, and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals.

Abstract: Exemplary embodiments of the invention provide a reference signal generator, system and method. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, a control voltage generator adapted to provide a temperature-dependent control voltage; and a plurality of variable reactance modules. The reference resonator generates a first reference signal having a resonant frequency, and each reactance module is adapted to modify a corresponding reactance in response to the control voltage to maintain the resonant frequency substantially constant or within a predetermined variance over a predetermined temperature range. A frequency controller may also be included to maintain substantially constant a magnitude of a peak amplitude of the first reference signal and maintains substantially constant a common mode voltage level of the reference resonator.

Abstract: A communication system includes a packet switch that routes data packets between endpoint devices in the communication system through virtual channels. The packet switch includes output ports each having a link bandwidth for outputting data packets. Each virtual channel is associated with an output port and is allocated a portion of the link bandwidth of the output port. The packet switch receives a data packet identifying a virtual channel at an input port, selects another virtual channel associated with the input port, routes the data packet through the packet switch, and outputs the data packet from the packet switch by using the selected virtual channel. Additionally, the packet switch may select a reliable transmission protocol, a continuous transmission protocol, or a pseudo-continuous transmission protocol for outputting the data packet from the packet switch. In some embodiments, the packet switch modifies the data packet to indicate the selected virtual channel.

Abstract: A multi-package module that includes a multi-layer interconnect structure, a housing structure attached to the multi-layer interconnect structure, and a plurality of integrated circuit packages inserted into slots in the housing structure, and placed into contact with the multi-layer interconnect structure. The integrated circuit packages can be removed from the slots in the housing structure, thereby enabling testing and/or replacement of the integrated circuit packages.

Abstract: A delta-sigma fractional-N frequency synthesizer having a charge pump with error canceling circuitry eliminates a non-linear term from the charge pump transfer function. The charge pump includes a matched pair of charging current sources, each supplying a first current IP1 to a common node, when enabled. The charge pump also includes a matched pair of discharging current sources, each sinking a second current IN1 from the common node, when enabled. The error canceling circuitry includes a charging current source, which supplies a current equal to the second current IN1 to the common node, when enabled. The error canceling circuitry also includes a discharging current source, which sinks a current equal to the first current IP1 from the common node, when enabled. The charging and discharging current sources of the error canceling circuitry are both enabled when either one of the matched pairs of charging and discharging current sources is enabled.

Abstract: A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is developed on the MSB node. A compensation capacitor coupled to the MSB node has a compensation capacitance selected to offset the jump error voltage introduced by the parasitic capacitance. The compensation capacitor is enabled when all of the LSB capacitors are coupled to digital input signals having a logic ‘0’ state. Otherwise, the compensation capacitor is disabled (e.g., left in a floating state).

Abstract: A method and apparatus for adjusting PLL and/or DLL timing offsets have been disclosed.