Abstract: A dual-gate semiconductor structure including a first polysilicon layer that has a p-type region and an n-type region. The p-type region overlies the channel region of a p-channel transistor, and the n-type region overlies the channel region of an n-channel transistor. A second polysilicon layer is formed directly on the first polysilicon layer, and exhibits good adhesion with the first polysilicon layer. A metal silicide layer is deposited on the second polysilicon layer. The second polysilicon layer and the metal silicide layer are deposited in different chambers of the same equipment, without breaking vacuum (i.e., in situ). The upper surface of the second polysilicon layer is therefore relatively clean, thereby providing good adhesion between the metal silicide and second polysilicon layers. The second polysilicon layer, which is either undoped or doped with nitrogen, inhibits vertical migration of impurities in the first and second regions to the overlying metal silicide layer.

Abstract: In a buffer circuit a pull-up circuit causes an output terminal of the buffer circuit make a transition from a low voltage to a high, and a feedback circuit increases the rate of the transition during the part of the transition when the output terminal moves from the low voltage to a predesignated voltage, the predesignated voltage being a value between but different from the low and high voltages. In another buffer circuit powered by a power supply voltage, a pull-up transistor causes a signal at an output terminal of the buffer circuit make a transition from a low voltage to a high voltage, and a converter circuit converts the power supply voltage to a lower voltage, the lower voltage powering the pull-up transistor.

Abstract: The prevention of the formation of undesired defects formed during the etching of etched metal interconnect lines on an integrated circuit during an integrated circuit manufacturing process that involves laying down on a semiconductor wafer a thin film such as an anti-reflective coating (ARC) on a layer of metal to be patterned into the metal interconnects of the individual integrated circuits. To do this the anti-reflective coating layer is covered with an oxide layer prior to applying and patterning subsequent photoresist. The specific metalization layer disclosed can be of aluminum, copper or copper-aluminum alloy. The ARC as disclosed is a nitride layer, such as titanium nitride. The oxide may be formed on the ARC in a number of known ways and may be etched subsequently alone or in combination with the underlying ARC and metal after subsequent photoresist deposit upon the oxide layer.

Abstract: A CAM system is provided that includes a plurality of CAM arrays that are assigned different priority levels. Each CAM array generates a plurality of match control signals, wherein each of the CAM arrays asserts a match control signal for each detected match. The CAM system also includes a plurality of latch circuits, each being coupled to receive the match control signals from a corresponding CAM array. A latch control circuit is also coupled to receive the match control signals from the CAM arrays. In response, the latch control circuit causes one and only one of the latch circuits to latch the match control signals received from the corresponding CAM array. The latch circuit that latches the match control signals is the latch circuit corresponding with the highest priority CAM array to assert a match control signal. In one embodiment, the latch circuit is controlled by a latch enable signal. Power savings are realized because only one latch enable signal is asserted for any compare operation.

Abstract: A system and method for encoding and decoding data utilizes Walsh-Hadamard Transforms and inversion techniques to generate the possible minimum disparity values for the data to be encoded. A minimum disparity value is then selected that also provides sufficient transition density.

Abstract: The present invention concerns a testing object for use in the testing of a wafer clamp. Wafer clamps are used to hold wafers in position on etchers. If the wafer clamp is worn, the process yield drops due to the heating of the wafer and subsequent photoresist melting. The testing object passes wafer clamps having a sufficient wafer overlap distance, but fails wafer clamps without a sufficient wafer overlap distance.

Abstract: A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. During an internally-controlled power-up sequence, respective memory cells within an array block are initialized to a respective non-intermediate voltage before enabling, during an internal memory operation, bit line sense amplifiers associated with the array block. Internal memory operations may then be performed as a result of external memory cycle requests received by the integrated circuit. In an exemplary embodiment, as the memory cell plate is being established at its proper voltage, all memory cells are forced to a low voltage level by simultaneously driving every word line high and by forcing all bit lines to VSS using the bit line equilibration circuitry. The word lines are then brought back low, and the operating bit line equilibrate voltage is properly established.

Abstract: An improved method is provided for fabricating a cobalt silicide structure that includes the steps of: (1) forming a silicon structure, wherein a native oxide is located over a first surface of the silicon structure, (2) loading the silicon structure into a chamber, (3) introducing a vacuum to the chamber, (4) depositing a titanium layer over the first surface of the silicon structure, wherein the thickness of the titanium layer is selected to remove substantially all of the native oxide, (5) depositing a cobalt layer over the titanium layer, (6) depositing an oxygen impervious cap layer over the cobalt layer; and then (7) breaking the vacuum in the chamber, and (8) subjecting the silicon structure, the titanium layer, the cobalt layer and the cap layer to an anneal, thereby forming the cobalt silicide structure. The cap layer can be, for example, titanium or titanium nitride. The resulting cobalt silicide structure is substantially free from oxygen (i.e., oxide).

Abstract: A semiconductor integrated circuit suitable for use in an ESD protection circuit is disclosed. A substrate has an active region formed therein so as to define a P/N junction therebetween. An insulating region is formed near the surface of the substrate adjacent the active region thus defining an edge therewith. The active region includes a highly doped portion formed near the surface of the substrate and near the edge of the insulating region and a lightly doped portion formed below the highly doped portion and separated from the edge of the insulating portion. By moving the highly doped portion of the active region away from the insulating region, the P/N junction is effectively moved away from the insulating region.

Abstract: A CAM cell array is disclosed in which a comparator function is performed by incorporating a selected transistor of each CAM cell latch into a signal path extending between a match line and a second (e.g., charge or discharge) line. A first terminal of the selected transistor is connected to the match line (or the second line), a second terminal is connected to an internal node of the latch, and a gate terminal of the selected transistor is controlled by the data value stored in the latch. The internal node of the latch is connected through a control transistor having a gate terminal connected to receive an applied data value. When the applied data value is equal to the stored data value, the match line is coupled to the second line along a signal path passing through the selected transistor and the pass transistor. During programming (i.e., when data values are written to the latch), the match line (or second line) carries a low/high voltage signal needed to set (flip) the latch into a desired state.

Abstract: A priority encoding interface transmits data to the receiving device from a highest priority FIFO memory block that is selected from at least two of a plurality of FIFO memory blocks until the highest priority FIFO memory block is empty. The interface inhibits transfer of data to the data receiving device from remaining ones of the FIFO memory blocks, until the highest priority FIFO memory block is empty. Transmission of data from the highest priority FIFO memory block and inhibited transfer of data from remaining ones of the FIFO memory blocks, take place in response to an indication from the data receiving device that the data receiving device is enabled to receive data from the at least two of the FIFO memory blocks.

Abstract: A CAM array including volatile or non-volatile ternary CAM cells that discharge their associated match line through a special discharge line (e.g., a low match line), instead of through the bit line, is disclosed. Each ternary CAM cell includes a pair of storage elements that are used to store a data bit value, a comparison element that is used to compare the stored value with an applied data value, and a discharge element that is coupled between the discharge line and the match line. During operation, when the applied data value matches the stored value, the discharge element de-couples the discharge line from the match line (i.e., a high voltage on the match line remains high). Conversely, when the applied data value does not match the stored value, the discharge elements couple the discharge line to the match line, thereby discharging the match line to the discharge line.

Abstract: Implanted regions, formed in a semiconductor substrate by ion implanting oxygen or nitrogen ions, are converted to dielectric isolation regions by high temperature annealing. In some embodiments, oxygen and/or nitrogen ions are implanted at multiple predetermined depths to provide a graded implant profile in the implanted regions. In some embodiments, oxygen and/or nitrogen ions are implanted to have a peak concentration at a predetermined depth in the implanted regions. High temperature annealing is performed in an inert atmosphere or in an atmosphere having trace amounts of oxygen present for some or all of the anneal time.

Abstract: A CAM array includes non-volatile ternary CAM cells that use access transistors to easily read from and write to the non-volatile transistors. Each ternary CAM cell includes a pair of storage elements that are used to store a data bit value, and an access element that is used during CAM array operation. During a comparison operation, when the applied data value matches the stored value, the storage elements de-couple the match line from a discharging bit line (i.e., a high voltage on the match line remains high). Conversely, when the applied data value does not match the stored value, the storage elements couple the match line to a discharging bit line, thereby discharging the match line.

Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Abstract: A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line, and providing an indicator signal to the bus to indicate which polarity form of the data word is driven onto the bus. The data word and the indicator signal may be received from the bus, and the polarity form of the data word is conditionally inverted in response to the indicator signal. A noise reduction system includes, for one embodiment, a sending circuit which compares each bit of a data word to be next communicated onto the bus against a corresponding bit of the present data word on the bus. If more than half the bits differ, then the next data word is inverted to form a complement next data word.

Abstract: A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO memory device to permit selection of a wide range of cell sizes. The variable cell size circuit controls successive accesses to a cell in the memory device, and it resets a byte count when the byte: count equals the cell size value to initialize the circuit for a subsequent access operation. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access. An alignment circuit generates data for write operations in cells that store an odd number of bytes per cell to compensate for the two byte per cell read operations. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading.

Abstract: Integrated circuit output buffers include pull-down an pull-up circuits and a control circuit that utilizes a preferred feedback circuit to facilitate a reduction in simultaneous-switching noise during pull-down and pull-up operations and also improve the impedance matching characteristics of the output buffers during DC conditions. The preferred feedback circuit also limits the degree to which external noise can influence operation of the control circuit. Each of the pull-down and pull-up circuits may comprise a respective pair of primary and secondary transistors. The pull-down circuit is preferably configured so that the primary and secondary pull-down transistors (e.g., NMOS transistors) are electrically coupled to an output signal line (through an ESD protection resistor) and a first reference signal line (e.g., Vss).

Abstract: A high performance random access memory integrated circuit is disclosed in several embodiments, along with various embodiments of associated supporting circuitry, which offers significant power savings in read operations. The integrated circuit is capable of retrieving data words from a memory array either one data word in a single clock cycle or more than one data word in a single clock cycle. For random memory reads, retrieving one data word from the memory array in a clock cycle where the memory array is accessed in response to each read request saves power over retrieving more than one data word from the memory array in the clock cycle. Conversely, if read requests are burst requests (i.e., a first read request immediately followed by advance requests), power is saved by retrieving more than one data word in a clock cycle where the memory array is accessed.

Abstract: Clock recovery circuits and methods include a first phase locked loop that generates a control signal in response to a reference clock. A pulse generating and delaying circuit is responsive to the input data signal to generate from the input data signal pulses of predetermined width that are delayed by a predetermined delay. A second phase locked loop is responsive to the control signal, to the pulse generating and delaying circuit and to a mode signal, to generate a clock signal from the input data signal. Accordingly, only the first phase locked loop need include a reference clock. Moreover, in an integrated circuit that includes multiple data ports, only the pulse generating and delaying circuit and the second phase locked loop may need to be duplicated for each data port, to allow each data port to operate at a frequency that is independent of the other data ports. A common first phase locked loop, including a common reference clock, may provide a common control signal to all data ports.