Abstract: In accordance with the present invention is provided a system and method for improving a timestamp precision in a precision timestamp protocol (PTP) device. The present invention provides for dynamic adjustment of otherwise uncertainty of the latency of a connection between two devices connected together through a gearbox and/or a block sync circuit. The dynamic adjustment is accomplished by identifying the alignment of data within the gearbox and block sync and adjusting the timestamp assigned to the data based upon the identified alignment to remove the jitter associated with the gearbox and the block sync, thereby improving the timestamp precision in the PTP device. In a particular embodiment, the invention is employed in a serial-deserializer (SERDES) device.

Abstract: A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is disclosed. Use of a circular-reorder queue (CRQ) for both ingress and egress allows packet reordering and packet passing.

Abstract: A touch sensor includes conductive elements of substantially concave shape to enable detection of multiple simultaneous touches in at least two directions, with reduced noise sensitivity and enhanced accuracy. The shapes of the conductive elements may be similar, or may be alternating, complementary shapes that cover substantially all of the sensor area. The conductive elements physically interact with adjacent elements in such a way that the area covered by a touch changes monotonically from overlapping substantially all of one element to overlapping substantially all of an adjacent element as the touch area is moved from one element to the other element along a line between the centers of those adjacent elements. Such monotonic change of touch overlap area may occur simultaneously in two orthogonal directions. Connections from internally positioned conductive elements to a touch controller may be made to pass through other conductive elements.

Abstract: An inductive wireless power transfer device comprises a transmitter that comprises a transmit coil configured to generate a wireless power signal to a coupling region in response to an input voltage, and a modulator configured to modulate the wireless power signal and encode data with the wireless power signal to establish a back-channel communication link from the transmitter to a receiver. An inductive wireless power receiving device comprises a receiver that comprises a receive coil configured to generate a time varying signal in response to receiving a modulated wireless power signal from a transmitter in a coupling region, and a demodulator configured to demodulate the modulated wireless power signal from an established back-channel communication link from the transmitter to a receiver. Related inductive wireless power transfer systems and methods for back-channel communication from the transmitter to the receiver of an inductive wireless power transfer system are disclosed.

Abstract: A timing controller includes a pipelined delay chain configured to process commands and control signals associated with the commands between a first device and a plurality of second devices having different timing requirements. The pipelined delay chain includes a cascaded arrangement of a primary delay chain, at least one secondary delay chain and a plurality of control signal sequence generators responsive to signals generated by the at least one secondary delay chain. The primary delay chain may include a plurality of serially-linked registers configured to support a pipelining of the commands and a stack configured to support operations to push and pop the control signals associated with the commands to and from the stack.

Abstract: Temperature accuracy is improved, conversion gain is increased without increasing current density and parasitic resistance errors and other problems with conventional bandgap reference temperature sensors are eliminated by generating a signal proportional to temperature from three samples, where the signal is defined as a difference between a first difference and a second difference, the first difference comprising a difference between a second sample and a first sample, the second difference comprising a difference between a third sample and the first sample, and where the signal is defined to cancel parasitic components in the first, second and third samples.

Abstract: A method and apparatus for congestion and fault management with time-to-live (TTL) have been disclosed. Each time a packet is transferred into an Egress Port's Final Buffer, an associated TTL Timeout Counter will be loaded with a value. If the packet cannot be transferred out of the Egress Port before TTL timeout, it will be purged by removing a memory buffer pointer from the corresponding Virtual Output Queue (VOQ) entry.

Abstract: Systems and methods are disclosed for managing power consumption in electronic devices. In certain embodiments, an integrated circuit for managing power consumption in an electronic device includes an input/output (I/O) interface, a first circuit block coupled to the I/O interface, and an interface circuit coupled between the I/O interface and the first circuit block, the interface circuit configured to provide a defined logic state to the first circuit block or a second circuit block external to the integrated circuit if one of the first circuit block or the second circuit block is powered down. By providing a defined logic state to the first circuit block or the second circuit block when one of the first circuit block or the second circuit block is powered down, power consumption of the electronic device may be reduced.

Abstract: Integrated circuit devices include first and second periodic signal generators and a power down detection circuit. The first periodic signal generator is configured to generate at least a first periodic signal having a first frequency at an output thereof and the second periodic signal generator is configured to generate a second periodic signal having a second frequency less than the first frequency at an output thereof. The power down detection circuit is configured to selectively provide one or the other of the first and second periodic signals to an output terminal of the integrated circuit device, in response to monitoring a status of a signal received at an input terminal of the integrated circuit device. This received signal reflects a power down status of an external device that receives the selected one of the first and second periodic signals.

Abstract: A method and apparatus for unified final buffer with pointer-based and page-based scheme for traffic optimization have been disclosed.

Abstract: Integrated circuit devices may utilize automatic methods for adjusting the tail currents of current mode logic (CML) cells, which compensate for variations in process corners and thereby enable reliable operation of high performance circuits, such as frequency synthesizers. An integrated circuit may include a current mode logic (CML) circuit responsive to at least one input signal and a variable current source electrically coupled to the CML circuit. This variable current source can be configured to sink (or source) a first current from (or to) the CML circuit in response to a control signal. A control circuit may also be provided, which is configured to generate the control signal in response to a process corner indication signal. This process corner indication signal, which may be generated by a process corner detection circuit, preferably has a magnitude that estimates a relative speed of a process corner associated with the integrated circuit device.

Abstract: A Method and Apparatus for Channel Equalization in High Speed S-RIO based Communication Systems have been disclosed. By adjusting equalizer coefficients based on 8B10B error counts and an error threshold, a receiver may be dynamically adjusted. By adjusting transmitter pre-emphasis based on 8B10B error counts and an error threshold, a transmitter may be dynamically adjusted. Both the transmitter and receiver may be adjusted dynamically based on 8B10B error counts and different error thresholds.

Abstract: A circuit is disclosed to enhance slew rate of an amplifier. An amplifier includes an output, a first input, and a second input in a differential pair configuration. A slew rate enhancer includes a first slew rate enhancer and a second slew rate enhancer. The first slew direction enhancer is configured to detect a first slew rate condition in a first direction responsive to the first input and the second input and provide additional current for a first side of the differential pair of the amplifier during the first slew rate condition. The second slew direction enhancer is configured to detect a second slew rate condition in a second direction responsive to the first input and the second input and provide additional current for a second side of the differential pair of the amplifier during the second slew rate condition.

Abstract: A charging system includes a temperature sensor to generate a temperature signal responsive to a temperature of an energy storage device. A circuit temperature sensor generates a circuit temperature signal responsive to a temperature of a semiconductor device. A charge adjuster generates a desired current signal responsive to the temperature signal and the circuit temperature signal. A comparator compares a charge-current level signal to the desired current signal to generate a charge adjustment signal. A charge controller on the semiconductor device generates and adjusts a current of a charging signal for charging the energy storage device responsive to the charge adjustment signal. The charge adjuster may generate a reduction signal when the temperature signal is above a throttle threshold, reduce a digital desired current signal responsive to the reduction signal, and convert the digital desired current signal to the desired current signal as an analog signal.

Abstract: A periodic signal generator includes a resonant LC tank circuit that generates a periodic reference signal at a first frequency at a differential output thereof. A temperature-responsive frequency compensation module is electrically coupled to the differential output of the resonant LC tank circuit. This module includes a temperature dependent voltage control module that generates a temperature dependent control voltage and an array of switchable capacitive modules that is electrically coupled to a first node of the differential output of the resonant LC tank circuit and responsive to the temperature dependent control voltage and a plurality of switching coefficients. The array of switchable capacitive modules includes a fixed capacitor having a first terminal electrically coupled to the first node and a voltage-controlled variable capacitor having a first terminal electrically coupled to the first node.

Abstract: A test assembly (12) for testing a device (10) having a heat spreader (20), a package substrate (18) having a substrate ground (18G), and a grounding conductive segment (44A), includes (i) an input conductive segment (38) that is electrically connected to the heat spreader (20), (ii) a test board (28) having a board ground (30), and (iii) a control system (34) that is electrically coupled to the input conductive segment (38) and the board ground (30). During testing, the device (10) is positioned so that the substrate ground (18G) is electrically connected to the board ground (30). Additionally, the control system (34) directs a test current to one of the input conductive segment (38) and the board ground (30) to test the effectiveness of the grounding conductive segment (44A) including a first electrical interface (45A).

Abstract: A multiple time domain synchronizer includes a data pipeline containing a plurality of serially-connected delay elements therein. A latency selection circuit is provided, which has a plurality of inputs electrically coupled to outputs of a corresponding plurality of delay elements in the data pipeline. The latency selection circuit is configured to pass a data pipeline signal from an output of a selected one of the plurality of delay elements in response to a latency control signal. A synchronization circuit is provided, which is electrically coupled to an output of the latency selection circuit. This synchronization circuit, which includes first and second unequal timing paths therein, is responsive to a clock that synchronizes capture of the data pipeline signal selected by the latency selection circuit and a destination code that selects one of the first and second unequal timing paths to be traversed by the captured data pipeline signal as active.

Abstract: Oscillator circuits include a MEMs resonator, a variable impedance circuit (e.g., varistor) and an adjustable gain amplifier. The variable impedance circuit includes a first terminal electrically coupled to a first terminal of the MEMs resonator and the adjustable gain amplifier is electrically coupled to the variable impedance circuit. The adjustable gain amplifier may have an input terminal electrically coupled to the variable impedance circuit and a second terminal of the MEMs resonator may receive, as feedback, a signal derived from an output of the adjustable gain amplifier. A Q-factor control circuit may be provided, which is configured to drive the variable impedance circuit and the adjustable gain amplifier with first and second control signals, respectively, that cause an impedance of the variable impedance circuit and a gain of the adjustable gain amplifier to be relatively high during a start-up time interval and relatively low during a post start-up time interval.

Abstract: Methods of forming micromechanical resonators include forming first and second substrates having first and second semiconductor layers of first and second conductivity type therein, respectively. The first semiconductor layer of first conductivity type is bonded to the second semiconductor layer of second conductivity type to thereby define a first rectifying junction at an interface of the bonded semiconductor layers. A piezoelectric layer is formed on the first rectifying junction and at least a first electrode is formed on the piezoelectric layer.

Abstract: A circuit for linearizing a power amplifier. The circuit includes a main signal path comprising a digital-to-analog converter, wherein a main signal is transmitted through the main signal path to said power amplifier; and a digital pre-distortion path disposed outside of the main signal path, wherein the digital pre-distortion path includes a digital pre-distorter for digitally pre-distorting the main signal.