Abstract: In a distributed antenna system (DAS) and a local area network (LAN), a common communication infrastructure distributes data from radio-based and Internet-based sources. A radio equipment (RE) of the DAS interfaces to a LAN segment. For the downlink, a gateway maps radio signal data from a radio equipment controller (REC) and data packets from a switch to mixed-data frames using a radio data interface protocol for transmission in the DAS. At the RE, the signal data and data packets are retrieved from the mixed-data frames and provided to the air interface and LAN segment, respectively. For the uplink from the RE, the radio signal data from the air interface and the data packets from the LAN segment are mapped to mixed-data frames and transmitted to the gateway. The gateway retrieves the signal samples and data packets from the mixed-data frames for transfer to the REC and switch, respectively.

Abstract: A package that electrically connects an integrated circuit to a printed circuit board includes a frame and a package body that encases a portion of the frame and the integrated circuit. The frame includes a mounting region that is connected to the printed circuit board, and a cantilevering region that cantilevers away from the mounting region. The cantilevering region retains the integrated circuit in a flexible fashion.

Abstract: The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).

Abstract: Methods of testing packaged thin-film piezoelectric-on-semiconductor (TPoS) microelectromechanical resonators having hermetic seals include measuring a quality factor (Q) of resonance of the packaged resonator at at least two unequal temperatures to determine whether a ?Q/?T is significantly different (e.g, by at least 50%) over a temperature range (?T) spanning a smallest and largest of the at least two temperatures. These measurements are performed for a packaged resonator having a QAIR<QTED, where QAIR is the quality factor of resonance of the packaged resonator due to air damping and QTED is the quality factor of resonance of the packaged resonator due to thermoelastic damping.

Abstract: Systems, devices, and methods for providing backup power to a load are disclosed. A power converter may comprise a capacitor array comprising a plurality of capacitors and configured to store a charge from an input during a charge mode of operation and provide a charge to an output during a discharge mode of operation. Further, the power converter may comprise a controller configured to selectively couple the capacitor array to the input during a portion of the charge mode of operation and selectively couple the capacitor array to the output during a portion of the discharge mode of operation.

Abstract: A microelectromechanical resonator includes a resonator body anchored to a substrate by at least a pair of tethers that suspend the resonator body opposite an underlying opening in the substrate. A first thermally-actuated tuning beam is provided, which is mechanically coupled to a first portion of the resonator body that is spaced apart from the pair of tethers. The first thermally-actuated tuning beam is configured to induce a mechanical stress in the resonator body by establishing a thermal expansion difference between the first thermally-actuated tuning beam and the resonator body in response to a passing of current through the first thermally-actuated tuning beam.

Abstract: Energy sharing circuits and related methods are disclosed herein. A high voltage can be selectively coupled to a first source line and a low voltage can be selectively coupled to a second source line during a first time period. During a subsequent time period, a first coupling switch is activated to inductively couple the first source line to the second source line and diode block the second source line from the first source line. During a subsequent time period, the low voltage is selectively coupled to the first source line and the high voltage is selectively coupled to the second source line. During a subsequent time period, a second coupling switch is activated to inductively couple the second source line to the first source line and diode block the first source line from the second source line.

Abstract: A serial buffer transports packets through queues capable of operating in a packet mode or a raw data mode. In packet mode, entire packets are stored in a queue. In raw data mode, packet header/delimiter information is not stored in the queue (only packet data is stored). Packets can be transferred out of a queue in response to a slave read request. The serial buffer constructs a packet header in response to the slave read request, and retrieves a specified amount of packet data from the selected queue. The serial buffer also transfers out packets as a bus master when a water level exceeds a water mark within a queue. The serial buffer constructs packet headers for these bus master transfers, which may be performed in a flush mode or a non-flush mode (in packet mode), or in a flush mode (in raw data mode).

Abstract: An integrated circuit metal oxide metal (MOM) variable capacitor includes a first plate; one or more pairs of second plates positioned on both sides of the first plate; one or more pairs of control plates positioned on both sides of the first plate and positioned between the pairs of second plates; and a switch coupled to each control plate and a fixed potential.

Abstract: Systems and methods are disclosed for performing data conversion by matching current sources using a thin oxide device; and minimizing voltage stress on the thin oxide device during operation or power down.

Abstract: A microelectromechanical resonator includes a resonator body, which is encapsulated within a sealed cavity extending between first and second substrates that are bonded together. The resonator body is anchored to the first substrate by at least a pair of tethers that suspend the resonator body opposite an underlying recess in the first substrate. A resistive heating element is provided, which is configured to indirectly heat the resonator body through convective heating of the cavity. This resistive heating element may be disposed on an inner surface of the second substrate that is exposed to the cavity. The resonator may also include first and second electrical interconnects, which extend through the second substrate and contact respective first and second portions of the resistive heating element.

Abstract: A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block.

Abstract: An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.

Abstract: A frequency synthesizer includes a frequency generator configured to generate a periodic output signal in response to a periodic input signal and a temperature-dependent code. A temperature sensor is provided, which is configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the frequency synthesizer. A control circuit is provided, which is configured to generate the temperature-dependent code in response to the temperature measurement signal and a plurality of clocks having unequal frequencies. The control circuit can include a cascaded arrangement of an oversampled data converter and a digital filter, which are sequentially responsive to first and second ones of the plurality of clocks during generation of the periodic output signal by the frequency generator.

Abstract: A frequency synthesizer is configured to generate a periodic output signal in response to a periodic input signal and a temperature-dependent frequency adjusting control signal. A temperature sensor is provided, which is configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the frequency synthesizer. A control circuit is provided, which is configured to generate the temperature-dependent frequency adjusting control signal in response to the temperature measurement signal. This control circuit includes a cascaded arrangement of an oversampled data converter and a multi-stage digital filter, which is configured to generate a plurality of codes from respective ones of the digital filter stages, and a selection circuit, which is configured to use at least first and second ones of the plurality of codes in sequence during first and second consecutive time intervals to generate the temperature-dependent frequency adjusting control signal.

Abstract: Microelectromechanical resonators include a resonator body with a built-in piezoelectric-based varactor diode. This built-in varactor diode supports passive frequency tuning by enabling low-power manipulation of the stiffness of a piezoelectric layer, in response to controlling charge build-up therein at resonance. A resonator may include a composite stack of a bottom electrode, a piezoelectric layer on the bottom electrode and at least one top electrode on the piezoelectric layer. The piezoelectric layer includes a built-in varactor diode, which is defined by at least two regions having different concentrations of electrically active dopants therein.

Abstract: A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array.

Abstract: A method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer (RT) and continuous transfer (CT) modes have been disclosed where outstanding packets to be processed is through a Retransmission Mapper with a VOQ read pointer realignment that can quickly optimize network traffic with multiple VCs and mixed RT/CT modes.

Abstract: Fractional-N divider circuits include a multi-modulus divider, which is configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof. This division is performed in response to an overflow signal received at a second input thereof, where N is an integer greater than one. A phase correction circuit is configured to generate a second reference signal in response to a divider output signal generated by the multi-modulus divider. A divider modulation circuit is provided, which is configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by the multi-modulus divider. The divider modulation circuit includes a segmented accumulator, which is configured to generate a plurality of segments of a count value having at least one period of latency therebetween.

Abstract: An apparatus includes an adjustable oscillator circuit configured to generate an output signal having a frequency that varies responsive to a frequency control signal and a frequency reference generator circuit configured to produce a frequency reference signal. The apparatus further includes a calibration circuit configured to determine a relationship of the output signal to the frequency reference signal and to enable and disable the frequency reference generator circuit based on the determined relationship.