Abstract: In accordance with some embodiments, a transmitter for wireless transfer includes a rectifier that receives an AC voltage and provides a DC voltage; a capacitor that receives and smooths the DC voltage; a regulator that receives the DC voltage and outputs an input voltage; and a wireless transmitter that receives the input voltage and transmits wireless power.

Abstract: An apparatus comprises a plurality of driver circuits and a control registers block. The plurality of driver circuits may be configured to drive a read line in response to a memory signal and a reference voltage. The control registers block generally configures the plurality of driver circuits to implement an asymmetric voltage swing of the read line about a voltage level that is half of the reference voltage.

Abstract: A Method and Apparatus for a Transmission Gate for Multi-GB/s Application have been disclosed. By actively biasing the gate and body of both NFET and PFET improved performance is achieved.

Abstract: Operation of a PCIe Retimer over an Optical Cable has been disclosed. In one implementation a Optical Idle ordered set (OIOS) is introduced as well as a high Z ordered set (HZOS).

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an intermediate signal in response to an input clock signal operating at a frequency. The first circuit may modify the input clock signal according to a threshold frequency to generate a waveform for the intermediate signal. The waveform of the intermediate signal may have at least one of (i) pulses and (ii) a steady state. The second circuit may be configured to generate a control signal in response to the intermediate signal. The second circuit may modify the intermediate signal to generate the control signal. The control signal may have a first state when the intermediate signal has pulses. The control signal may have a second state when the intermediate signal has the steady state.

Abstract: A method and apparatus provides a parameter estimation processor configured to estimate parameters used to compress data for transmission over a serial data link. The parameter estimation processor includes a processor. The processor includes user programmable inputs. The user programmable inputs set an input data packet length, a target compression ratio, and a resampling factor and allow filter parameters to be set. Input data information is received from an input data buffer of a data sample compressor. The processor performs a function that: (a) adjusting a target compression ratio by a first compression ratio to determine a remaining compression ratio when the resampling operation is enabled; (b) estimating a set of compression parameters that are used to achieve the remaining compression ratio, the set of compression parameters includes an attenuation value, filter order, a type of encoding; and (c) sends the set of compression parameters to the data sample compressor.

Abstract: A wireless power transmitter may include a transmit coil configured to generate a wireless power signal for wireless power transfer, at least one secondary sensing coil configured to generate a signal responsive to a magnetic flux field generated during the wireless power transfer, and control logic configured to detect at least one condition of a wireless power transfer system responsive to detecting distortion in the magnetic flux field from the at least one signal received from the secondary sensing coil. A related method may include generating with a wireless power transmitter a wireless power signal, generating with a plurality of secondary sensing coils one or more signals responsive to a magnetic flux field generated during the wireless power transfer, and detecting at least one condition of a wireless power transfer system responsive to the one or more signals generated by the plurality of secondary sensing coils.

Abstract: A Process Compensated Delay has been disclosed. In one implementation delay is primarily based on electron mobility.

Abstract: An apparatus comprising a first circuit, a second circuit and a channel decoder. The first circuit may comprise (i) a controller port and (ii) a plurality of memory ports. The second circuit may comprise (i) input port and (ii) a plurality of output ports. The channel decoder may be configured to decode a selection signal. The channel decoder may be configured to select (i) one of the plurality of memory ports and (ii) one of the plurality of output ports in response to the decoded selection signal. The selection signal may be received by the controller port and the channel decoder in a first mode. The selection signal may be received by the input port and the channel decoder in a second mode.

Abstract: A constant impedance switch dynamically manages switch impedance to eliminate or substantially reduce impedance glitches during switching events by stepping variable impedances through sequences of impedance values. As a result, VSWR may be reduced to or near 1:1, allowing programming and circuitry to be simplified. Switch impedance may be maintained for single and multi-throw switches having variable impedances of any order. Each variable impedance may comprise one or more configurable cells, subcells and elements controlled by thermometer, binary, hybrid or other coding technique.

Abstract: Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition.

Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal in a period determined by (i) an output clock signal and (ii) a second code. The second code may be variable. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal (i) in response to the third code and (ii) within an accuracy determined the second code.

Abstract: An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit and (ii) adjust a delay of transferring a data signal through the apparatus in response to (a) the delay amount and (b) the in-phase clock signal. The data signal may be received from the memory interface. The delay of transferring the data signal may be implemented to keep a latency of a data transfer within a pre-defined range.

Abstract: A wireless power receiver may include a receive coil configured to generate an AC power signal, at least one secondary sensing coil configured to generate a measurement signal responsive to a magnetic flux field, and control logic configured to detect at least one condition of a wireless power transfer system responsive to detecting distortion in the magnetic flux field from the at least one measurement signal received from the secondary sensing coil. A related method may include receiving with a wireless power receiver a wireless power signal for wireless power transfer from a wireless power transmitter, generating with a plurality of secondary sensing coils one or more measurement signals responsive to a magnetic flux field generated during the wireless power transfer, and detecting at least one condition of a wireless power transfer system responsive to the one or more measurement signals generated by the plurality of secondary sensing coils.

Abstract: A system and method for clock phase alignment at a plurality of line cards over a backplane of a communication system. Phase adjustments are continually made for the clock signals at the line cards by dynamically measuring the propagation delay between the timing device and each of the plurality of line cards and continuously communicating the appropriate phase adjustment to each of the plurality of line cards.

Abstract: Examples described include transport stream multiplexers that may not need to search for an appropriate source to use to generate a transport stream packet. Instead, the source to use may be indicated by a position (e.g. an entry) in a memory table, e.g. a metadata array. Methods for placing transport stream packets on a transport stream and initializing the metadata array are also described.

Abstract: An e-band transceiver includes a transmitter circuit and a receiver circuit. The transmitter circuit includes a surface mounted technology (SMT) module on which is mounted a silicon-germanium (SiGe) bipolar plus CMOS (BiCMOS) converter, a gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) output amplifier coupled to the SiGe BiCMOS converter, and a microstrip/waveguide interface coupled to the GaAs pHEMT output amplifier. The receiver circuit of the e-band transceiver includes a receiver-side SMT module on which is mounted a receiver-side SiGe BiCMOS converter, a GaAs pHEMT low noise amplifier coupled to the receiver-side SiGe BiCMOS converter, and a receiver-side microstrip/waveguide interface coupled to the receiver-side GaAs pHEMT low noise amplifier.

Abstract: A method and apparatus for a novel adaptive equalization technique for a Serializer/Deserializer receiver is disclosed. In one approach, adjustment of AC and DC gains is performed before DFE coefficients are adjusted. Further after the equalization an electrical idle threshold may be set based on the results of the equalization.

Abstract: An apparatus includes a switching circuit and a plurality of registers. The switching circuit may be configured to generate a plurality of control signals in response to an enable signal. One control signal at a time may be active while the enable signal is in a transfer state. The registers may be configured to (i) buffer a plurality of setting values received from a memory and (ii) present the setting values from a subset of the registers to a plurality of transceiver circuits while a corresponding control signal is active. The setting values may include a plurality of phase values and a plurality of gain values used in the transceiver circuits to steer a radio frequency beam. Each transceiver channel may update the setting values from the registers within a predetermined time after a corresponding control signal becomes active.

Abstract: An apparatus includes an input port, an output port, a common port, a first impedance matching network, a second impedance matching network, a first switch circuit, and a second switch circuit. The first impedance matching network may be coupled between the input port and the common port. The second impedance matching network may be coupled between the common port and the output port. The first switch circuit may be coupled between the input port and a circuit ground potential. The second switch circuit may be coupled between the output port and the circuit ground potential. The first and the second impedance matching networks are asymmetrical.