Abstract: A voltage regulator includes an amplifier to generate a difference voltage responsive to a comparison of a reference voltage and a feedback voltage. An output driver is coupled to the amplifier and drives a regulated output voltage responsive to the difference voltage. An impedance circuit is coupled between the output driver and a low power source and establishes the feedback voltage responsive to a current through the impedance circuit. A variation detector is operably coupled between the regulated output voltage and the difference voltage and is configured to modify the difference voltage. In some embodiments, the difference voltage is modified responsive to a rapid change of the regulated output voltage capacitively coupled to the variation detector. In other embodiments, the difference voltage is modified responsive to a rapid change of the feedback voltage capacitively coupled to the variation detector.
Type:
Grant
Filed:
March 29, 2012
Date of Patent:
July 8, 2014
Assignee:
Integrated Device Technology, inc.
Inventors:
Shawn Wang, Yumin Zhang, Jeffrey G. Barrow
Abstract: A peripheral power management system includes a power monitor for determining a power consumption characteristic of a computing processor and a controller for generating a reference power signal based on the power consumption characteristic. The peripheral power management system also includes a power regulator control signal generator for generating a power regulator control signal based on the reference power signal. The power regulator control signal controls a peripheral device power regulator which regulates an electrical supply power of a peripheral device. In this way, the peripheral power management system controls regulation of the electrical supply power of the peripheral device based on the power consumption characteristic of the computing processor. In some embodiments, the peripheral power management system determines the power consumption characteristic of the computing processor by monitoring communication on a serial voltage identification bus.
Abstract: An integrated circuit device includes a reference voltage generator, which is configured to generate an adaptive reference voltage (Vref) that varies inversely relative to changes in magnitude of a data signal (DATA) received at an input thereof. This reference voltage generator includes a totem pole arrangement of at least two variable impedance elements having control terminals capacitively coupled (by respective capacitors) to the input. A current mirror is electrically coupled to the totem pole arrangement of at least two variable impedance elements. A comparator is also included. The comparator has a first input terminal that receives the adaptive reference voltage and a second input terminal that receives the data signal.
Abstract: A divider for use in an integrated circuit chip, such as a clock generator chip, includes a ramp generator circuit configured to generate a ramp signal and a synchronous detector circuit configured to receive the ramp signal and an input clock signal and to responsively control the ramp signal generator circuit to generate an output clock signal at an output of the synchronous detector circuit. In some embodiments, the synchronous detector circuit may include a voltage threshold detector circuit configured to receive the ramp signal and to generate a detection signal responsive thereto and a synchronous latch circuit having a clock input configured to receive the input clock signal and a data input configured to receive the detection signal. The synchronous latch circuit may be configured to control the ramp generator circuit.
Abstract: A power transistor and a power converter are disclosed that may improve the on-resistance and corresponding silicon area of a power transistor. The power transistor may comprise a drain, a source, and a channel therebetween divided into a plurality of transistor stripes, the plurality of transistor stripes being grouped in a plurality of different groups. The power transistor may further comprise a first top metal associated with one of the drain and the source, and a second top metal associated with the other of the drain and the source. The second top metal includes at least one portion that is coupled to different groups of transistor stripes. A related method for determining a layout topology of a power transistor is also disclosed.
Abstract: A synchronous rectifier circuit rectifies an AC input voltage to produce a DC output voltage. The synchronous rectifier circuit comprises MOSFET (metal-oxide-semiconductor field-effect transistor) switches coupled within secondary transformer windings resulting in a shortened AC current path compared to conventional synchronous rectifier circuits. The shortened current path mitigates skin and proximity effects, substantially improving the power efficiency of the synchronous rectifier circuit. A rectifier assembly integrates one or more synchronous rectifier circuits within a magnetic core.
Type:
Grant
Filed:
December 29, 2009
Date of Patent:
June 10, 2014
Assignee:
Integrated Device Technology inc.
Inventors:
Andrey Malinin, Anatoly Cherepakhin, Eric Allan Larson
Abstract: A periodic signal generator is configured to generate high frequency signals characterized by relatively low temperature coefficients of frequency (TCF). A microelectromechanical resonator, such as concave bulk acoustic resonator (CBAR) supporting capacitive and piezoelectric transduction, may be geometrically engineered as a signal generator that produces two periodic signals having unequal resonant frequencies with unequal temperature coefficients. Circuitry is also provided for combining the two periodic signals using a mixer to thereby yield a high frequency low-TCF periodic difference signal at an output of the periodic signal generator.
Abstract: Embodiments of the present disclosure include systems, apparatuses, and methods for dynamic frequency and voltage control of components used in a computer system. A system includes a processor voltage regulator and a system clock generator directly operably with each other. The processor voltage regulator provides a core voltage signal to a processor, and is configured to detect a present processor load state of the processor. The system clock generator is for providing a system clock signal to the processor. At least one of the processor voltage regulator or the system clock generator is further configured determine a desired frequency of the system clock signal responsive to the present processor load state, and determine a voltage level for the core voltage signal suitably paired with the desired frequency for proper operation of the processor at the desired frequency. Other systems, apparatuses, and methods are provided.
Type:
Grant
Filed:
August 31, 2010
Date of Patent:
May 20, 2014
Assignee:
Integrated Device Technology, Inc.
Inventors:
Ivan Hsiao, Eric Leung, Frank Matthews, Ordin Kuo, Dinh Bui, Duy Pham, Wallace Ly
Abstract: A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is disclosed. Use of a circular-reorder queue (CRQ) for both ingress and egress allows packet reordering and packet passing.
Type:
Grant
Filed:
October 31, 2010
Date of Patent:
May 20, 2014
Assignee:
Integrated Device Technology, Inc.
Inventors:
Mohammad Shahanshah Akhter, Zixiong William Wang, David Clifton Bond, Gregory Edward Lund
Abstract: A wireless power transmitter comprises a bridge inverter including a first switch and a second switch coupled together with a first switching node therebetween, and a first capacitor coupled to the first switching node. The transmitter further includes control logic configured to control the first switch and the second switch according to an operating frequency to generate an AC power signal from a DC power signal, and a resonant tank operably coupled to the first switching node of the bridge inverter, the resonant tank configured to receive the AC power signal and generate an electromagnetic field responsive thereto. A method for operating the wireless power transmitter and a method for making the wireless power transmitter are also disclosed.
Abstract: A controlled headroom low dropout regulator (CHLDO) having an LDO with an input voltage provided by a capacitor. An incremental voltage is added to an output voltage of the LDO to create a reference voltage. The reference voltage is compared to the input voltage to determine when to couple/de-couple the capacitor with a current source. If the capacitor is coupled to the current source, the capacitor will charge only if the voltage driven by the current source exceeds the input voltage provided by the capacitor. When the input voltage developed on the capacitor exceeds the reference voltage, the capacitor is automatically de-coupled from the current source. Multiple CHLDOs can be charged from a single current source, wherein charging automatically proceeds from the lowest voltage CHLDO to the highest voltage CHLDO.
Abstract: An output driver that includes a pull-up network comprising a first plurality of resistive branches forming a first R-2R resistive ladder structure, wherein the resistive branches of the pull-up network are coupled to a high voltage supply through pull-up switching transistors. The output driver may further include a pull-down network comprising a second plurality of resistive branches forming a second R-2R resistive ladder structure, wherein the resistive branches of the pull-down network are coupled to a low voltage supply through pull-down switching transistors. The output driver includes a control circuit to selectively activate or deactivate each of the first plurality of resistive branches and to selectively activate or deactivate each of the second plurality of resistive branches.
Abstract: A combined touch sensor and light-emitting-diode (LED) driver comprises a touch sensor circuit configured to detect a touch, where the touch sensor circuit is coupled to a common node and configured to operate with a first operating voltage, an LED driver circuit configured to drive an LED if the LED is coupled to the common node, where the LED driver circuit is also coupled to the common node and configured to operate with a second operating voltage is higher than the first operating voltage, and an n-type field effect transistor (FET) connected in series between the common node and the touch sensor. The n-type FET prevents the higher operating voltage of the LED driver from affecting the operation of the touch sensor, when a port of the combined touch sensor and LED driver IC is used to drive an LED. The touch sensor may be a capacitance-to-digital converter.
Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.
Abstract: A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses baseband signal samples resulting from analog to digital conversion of a received analog signal followed by digital downconversion. The compressed signal samples are transferred over the serial data link to the baseband processor then decompressed prior to normal signal processing. For the downlink, the baseband processor compresses baseband signal samples and transfers the compressed signal samples to the RF unit. The RF unit decompresses the compressed samples prior to digital upconversion and digital to analog conversion to form an analog signal for transmission over an antenna. Compression and decompression can be incorporated into operations of conventional base stations and distributed antenna systems, including OBSAI or CPRI compliant systems.
Abstract: A clock receiver includes a capacitive coupling circuit for filtering out direct-current voltages from a differential clock signal. In this way, the capacitive coupling circuit rejects common-mode noise in the differential clock signal. The clock receiver also includes a bias circuit for establishing a bias voltage in the differential clock signal and a differential amplifier for amplifying the differential clock signal. Further, the differential amplifier generate a feedback differential clock signal and provides the feedback differential clock signal to the bias circuit for further rejecting common-mode noise in the differential clock signal. The feedback differential clock signal functions as a negative feedback signal for rejecting common-mode noise in the differential clock signal and as a positive feedback signal for amplifying the differential clock signal.
Type:
Grant
Filed:
July 2, 2009
Date of Patent:
April 8, 2014
Assignee:
Integrated Device Technology inc.
Inventors:
Liang Leon Zhang, Alejandro F. Gonzalez
Abstract: A controller, power converter, and a related method for secondary side control of a switch are disclosed herein. An embodiment of the present invention includes a controller. The controller comprises a drain to source voltage (VDS voltage) input configured to receive the VDS voltage of a transistor, a gate drive output configured to output a gate drive voltage to a gate of the transistor, and control logic configured to initiate a minimum on time signal independent of triggering the gate drive voltage to activate the transistor. A related method comprises comparing a VDS voltage of a transistor to a plurality of voltage threshold levels, driving a gate of the transistor when the VDS voltage crosses a predetermined voltage threshold, and asserting a minimum on time signal when the VDS voltage crosses another predetermined voltage threshold independent of driving the gate of the transistor.
Abstract: A method and apparatus for glitch-free switching of multiple phase clock have been disclosed where switching from one phase to another phase is done step-by-step to avoid generating a glitch.
Abstract: A periodic signal generator is configured to generate high frequency signals characterized by relatively low temperature coefficients of frequency (TCF). This generator may include an oscillator containing a pair of equivalent MEMs resonators therein, which are configured to support bulk acoustic wave and surface wave modes of operation at different resonance frequencies. Each resonator includes a stack of layers including a semiconductor resonator body (e.g., Si-body), a piezoelectric layer (e.g., AIN layer) on the resonator body and interdigitated drive and sense electrodes on the piezoelectric layer. The oscillator is configured to support the generation of first and second periodic signals having unequal first and second frequencies (f1, f2) from first and second resonators within the pair. These first and second periodic signals are characterized by respective first and second temperature coefficients of frequency (TCf1, TCf2), which may differ by at least about 10 ppm/° C.