Abstract: An integrated circuit package capable of improving signal quality is disclosed. The integrated circuit package comprises a first substrate, an integrated circuit chip attached on the first surface of the first substrate. This integrated circuit package further comprises a plurality of external terminals mounted on the first substrate and a plurality of first bonding pads mounted on the edge portion of the first surface of the first substrate and respectively connected to the corresponding external terminals. Also, the integrated circuit package further comprises a second substrate and a plurality of second bonding pads mounted on the second surface of the second substrate and connected to the first bonding pads formed on the first substrate. Furthermore, this integrated circuit package further comprises a plurality of passive components disposed on the second substrate.

Abstract: A personal computer (PC) main board is used for mounting therein a memory module, and the memory module is capable of mounting therein one selected from a first type of Dynamic Random Access Memory (DRAM) and a second type of DRAM. The PC main board includes a memory module slot for replacably inserting therein the memory module and providing an operation voltage thereto, a switch device electrically connected to the memory module slot for changing a switching mode to adjust the operation voltage and an electric interface mode of the memory module in response to the type of the memory module, and a chipset electrically connected to the memory module slot and the switch device for switching operation modes between the first type of DRAM and the second type of DRAM in response to the switching mode of the switch device.

Abstract: A local oscillator and logic circuit pulses the open winding of a brushless DC motor at start up and the back EMF is used to generate a voltage to boost the voltage available to the control circuit for optimizing performance when starting with low supply voltage. As the rotor of a motor rotates and the windings are commutated by the drive electronics there is generated in each winding a voltage caused by the collapse of the current and the inherent inductance of the winding. These voltages exceed the normal operating voltage of the motor. The energy in these voltages is used to generate a regulated power feed to the analogue circuitry of the control circuit at a suitable voltage level. During steady state conditions, when the motor is running, the commutation of the windings is continual and there is ample energy available to power analogue electronics, and, if required, associated digital electronics as well.

Abstract: A signal transmission device adapted to transmit an n-bit parallel digital signal is used for avoiding a transmission error. The device includes a detector for receiving a first and a second n-bit digital data consecutively occurred in the n-bit parallel digital signal, proceeding a first calculation to obtain a changed value, and outputting an indicating signal while the changed value is larger than a threshold, an encoder electrically connected to the detector for receiving the indicating signal and the second n-bit digital data, proceeding a second calculation, and outputting an encoded second n-bit digital data to reduce the changed value between the first n-bit digital data and the encoded second n-bit digital data below the threshold, and a decoder electrically connected to the detector and the encoder receiving the indicating signal and the encoded second n-bit digital data, proceeding a third calculation, and recovering the second n-bit digital data.

Abstract: A system is disclosed for speeding workpiece thoughput in low pressure, high temperature semiconductor processing reactor. The system includes apparatus for loading a workpiece into a chamber at atmospheric pressure, bringing the chamber down to an intermediate pressure, and heating the wafer while under the intermediate pressure. The chamber is then pumped down to the operating pressure. The preferred embodiments involve single wafer plasma ashers, where a wafer is loaded onto lift pins at a position above a wafer chuck, the pressure is rapidly pumped down to about 40 Torr by rapidly opening and closing an isolation valve, and the wafer is simultaneously lowered to the heated chuck. Alternatively, the wafer can be pre-processed to remove an implanted photoresist crust at a first temperature and the chamber then backfilled to about 40 Torr for further heating to close to the chuck temperature.

Abstract: An approach to enhance the noise immunity of high-speed digital signals by means of a resonance-free environment is developed. Resonance detuning is achieved by appropriately reshaping the layout of the power/ground planes. Resonant properties of the power distribution system, including resonant frequencies and field distribution profiles, were characterized with frequency-domain simulations. Analysis of the resonant field profiles reveals that the electric field distribution of the dominant mode normally concentrates in the vicinity of the plane edge. Therefore, resonance can be effectively tuned out of the operating frequency range through boundary configuring. In addition, it is shown that variation of the quality factor with the external probe position provides a means to monitor and construct the resonant field distribution. Physical mechanism responsible for this unique property is clarified from the perspective of probe coupling.

Abstract: A method for converting N-bit image data of a digital image into M-bit image data, in which N−M=K, K>0, is disclosed. The method is adapted to be used for dithering in an image processing system or a computer graphic system. For example, an N-bit red color value of each pixel of the digital image can be converted into an M-bit red color value by this method with little or no color deviation. According to the method, a difference of the most significant n bits and the least significant n bits of the N-bit image data of a pixel is used as a preliminary criterion for color value conversion, in which n is preferably equal to K. An apparatus for converting N-bit image data of a digital image into M-bit image data, in which N−M=K, K>0, is also disclosed. The apparatus includes a subtraction operator for realizing the difference of the most significant n bits and the least significant n bits of the N-bit image data of the pixel.

Abstract: A method of forming a STI structure. First, a substrate having a trench is provided. Next, a conformable silicon oxide layer is grown on the surface of the trench by wet oxidation using single wafer process to serve as a liner oxide layer. Thereafter, the substrate and the silicon oxide layer is in-situ annealed. Finally, an insulating layer is completely filled into the trench.

Abstract: A substantially noiseless fastening system for a carrying pack includes a flap attached to the shell of the carrying pack along one edge of the flap, a fastener button attached to the flap near a second edge of the flap, and a button receiver attached to the shell. The button receiver has a tapered interference fit slot terminating in a notch for receiving the fastener button, the slot narrowing towards the edge of the flap attached to the shell. The fastening system also includes a pouch attached to the shell, a locking channel attached to the pouch, and a locking groove attached to the shell. The pouch has an edge that forms an opening between the pouch and the shell, and the locking channel engages the locking groove in an interference fit to close the opening.

Abstract: A reverberation generation processor. The reverberation generation processor generates a specific auditory signal according to a predetermined virtual environment having characteristics of spatial dimension, sound reflection, and decline. The natural sequence generator generates a natural sequence having a predetermined number of items according to the characteristics of the virtual environment. The sequence adjusting device adjusts gains of the items and a time scale between the items of the natural sequence and outputs an audio signal. The filter processor filters a predetermined frequency band of the audio signal according to the characteristics of the virtual environment and divides the filtered audio signal into a high frequency audio signal and a low frequency audio signal. The high frequency reverberation generator transforms the high frequency audio signal to a high frequency reverberation signal.

Abstract: A method of forming shallow trench isolation in a semiconductor substrate. A hard mask having an opening is formed on the semiconductor substrate. The semiconductor substrate is etched through the opening to form a shallow trench. The semiconductor substrate is annealed in an ambient containing argon gas at a temperature of about 1150 to about 1200° C. for 1 to 2 hrs. An insulator is then formed on the hard mask to fill the shallow trench. The insulator is planarized while the hard mask is used as the polishing stop layer. Thereafter, the hard mask is removed to expose the upper surface of the semiconductor substrate and leave a shallow trench isolation.

Abstract: A flip chip assembly process forming an underfill encapsulant. The method includes providing a chip having an active surface and a plurality of conductive bumps arranged in array with a predetermined bump pitch thereon, providing a substrate having a surface, having a die-attaching region, having a plurality of pads with previously formed solder paste thereon, arranged in array with a predetermined pad pitch the same as the active surface, forming an encapsulant in the die-attaching region excluding the pads, using a stencil and screen printing, and attaching the chip onto the substrate resulted from one-to-one joining the conductive bumps and the pads. A tool forming an underfill encapsulant is includes a stencil having at least one printing region, including a plurality of openings, a plurality of covers arranged in array with a predetermined cover pitch, and a plurality of connecting devices, connecting every two neighboring covers, or each cover with other regions of the stencil.

Abstract: A method for forming a damascene structure. An insulating layer is deposited on a substrate. A capping layer and a hard mask layer are successively formed on the insulating layer. Subsequently, the hard mask layer is etched to form at least one opening using the capping layer as an etching stop layer. A conformable metal layer is formed over the hard mask layer and the surface of the opening, and the metal layer is then anisotropically etched to form a metal spacer over the sidewall of the opening. Next, the capping layer and the underlying insulating layer under the opening are etched to form a trench therein. Next, the hard mask layer and the metal spacer are removed. Finally, the trench is filled with the conductive layer to complete the damascene structure after the substrate is cleaned.

Abstract: A turbulent fluid, such as a flame, is examined using an array of infrared detector elements. The relationship between the thermal emissions received by different elements at different times is analysed, for example using correlation functions. This enables existence of a flame to be verified and the nature of the flame to be identified.

Abstract: A chip-packaging substrate and test method therefor. The chip-packaging substrate includes at least one package area and a connection area enclosed by and connected to the package areas. A test circuit is arranged within the connection area, passing through at least two wire layers and the insulation layer therebetween. The test circuit electrically connects the first electrodes. Failure of the chip-packaging substrate is detected when the test circuit is open between any two electrodes.

Abstract: A method for multi-threshold voltage CMOS process optimization. The method includes the steps of: providing a semiconductor substrate with a plurality of devices of different threshold voltages; establishing a plurality of types of timing models for a timing calculation; obtaining a static timing analysis report through the timing calculation; defining a large and a small setup time margin as a Tl and a Ts; changing the devices whose setup time margins are less than Ts to low threshold devices; changing the devices whose setup time margins are greater than Tl to high threshold devices; checking a setup time of each device; changing the devices whose setup time margin does not meet the enhanced static timing analysis report; performing a first pocket implant process for the normal threshold devices; performing a second pocket implant process for the low threshold devices and performing a third pocket implant process for the high threshold devices.

Abstract: A channel estimator for use in wireless local area networks (WLAN's), characterized in that a channel estimation controller with a simplified recursive least square (RLS) algorithm and a data-reconstructor are employed to adjust the channel response in frequency domain during the delivery of a signal packet. Such adjustment is adaptively performed at anytime during the delivery of a signal packet so as to achieve fast convergence as well as accurate channel estimation.

Abstract: The present invention provides an improved cardcage design. The improvements result from the formation of an integral cardcage side using a construction method involving precision punched sheet aluminum that is precision formed into final configuration. The integral cardcage side design provides ease of assembly for the cardcage while enhancing structural integrity, improves the alignment of circuit cards within the cardcage to the backplane, increases the airflow channels between the card guides, and adapts to incorporate additional features for airflow control. The manufacturability of the cardcage is greatly simplified by reducing the number of parts requiring assembly and by the use of simple and inexpensive tools and assembly techniques.

Abstract: A method of forming a salicide. A metal layer is formed on a silicon-based substrate comprising a gate with a spacer on the side wall of the gate and a source/drain is provided. Next, a first thermal treatment is performed to make the portions of the metal layer react with the silicon in the gate and the source/drain to form a salicide. Then, any unreacted metal and the spacer are removed. An ion containing silicon is introduced into the source/drain. Finally, a second thermal treatment is performed.

Abstract: A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.