Abstract: Magic Packet technique is developed to remotely awake a computer host in a sleeping mode on a node through computer network. Instead of utilizing a large amount of memory or a complex algorithm, an algorithm and system, which only utilize two sets of counters and control logics to perfectly detect the Magic Packet according to the characteristics of magic packet are disclosed. According to the present invention, if a LAN controller on a node of the network is in magic packet mode, it will detect all input frames addressed in the node to search a specific data sequence indicative of the Magic Packet frame. Once the controller detects the data sequence, it will notice the power management circuitry of the computer host on the sleeping node to awake the system.

Abstract: A signal processing technique applied to the readout of two-dimensional detector arrays provides a dynamic correction mechanism for the varying offsets of the different elements of the array. The outputs of the elements are supplied to an offset correction circuit operative to compensate for the differences in the d.c. or low frequency outputs from a predetermined voltage wherein a fraction of the difference is subtracted at each successive cycle to gradually reduce the difference.

Abstract: A stereo synchronizing signal generator for liquid crystal shutter glasses is provided. The stereo synchronizing signal generator includes a signal generating unit to generate preliminary shuttering signals according to an image vertical synchronizing signals and a start signal. A signal delaying unit is provided to delay the preliminary shuttering signals according to a value, which can be changed by users. Then an output unit is provided to transmit the delayed shuttering signals to the liquid crystal shutter glasses. Due to that the signal generating unit generates a predetermined shuttering signal, such as right eye shuttering signal, at the rise edge of the start signal, the shuttering signals can always match up to the right image. Furthermore, the signal delaying unit can adjust the timing of the shuttering signal according to the value of the register, therefore the shuttering signals can always be synchronized with the image.

Abstract: An interface device for the synchronous transfer of data over serial ATA. The link layer portion receives the data from a device. The status monitor detects the status of the link layer portion. The fix pattern generator provides primitive formats responding to the status of the link layer portion. The physical layer controller directly returns the primitive formats to the device without sending or receiving the primitive formats to the link layer portion.

Abstract: A method for reducing buffer requirements in a digital audio decoder. Firstly, N samples that have to be decoded for an audio channel at this time are extracted from a sub-frame of a bitstream. A sub-block of K PCM samples is calculated at a time by performing an inverse transform on the N extracted samples, and then the N extracted samples are discarded. Note that the number of extracted samples is greater than or equal to the number of the PCM samples in a generated sub-block, i.e., N≧K. The above steps are repeated until one PCM output sub-frame of the audio channel is fully obtained.

Abstract: An apparatus for calculating an exponential calculating result for a base 2 floating-point number comprises a transforming device, K exponential tables and a multiplier. The transforming device receives the floating-point number, transforms the floating-point number to an integer part and a fractional part and outputs the integer part and the fractional part. The fractional part is an N-bit number and divided into K parts which have N1, N2, . . . , NK bits respectively, wherein N=N1+N2+ . . . +NK. Each of the exponential tables receives one of the K parts divided from the fractional part and outputs a result. The multiplier receives all results from the exponential tables and outputs a mantissa. The integer part outputted form the transforming device is an exponent.

Abstract: An apparatus for computing a logarithm to a base p of a floating-point number X. The floating-point number X is represented in the format of (−1)Sx·2Ex·Mx, where Mx=(1+fx)=(1+Ax·2−K)+(Bx·2−N), where Sx is a sign, Ex is an exponent, Mx is a mantissa, 1≦Mx<2, fx is a N-bit fraction, Ax is a value of the most significant K bits of fx, Bx is a value of the least significant (N−K) bits of fx, 0≦K<N, and p, K, N are natural numbers. The apparatus includes: a first multiplier, a logarithmic table, a first adder, a divider, a Taylor-Series approximation circuit, a second multiplier, and a second adder.

Abstract: A partially embedded decoupling capacitor is provided as an integral part of a semiconductor chip for reducing delta-I noise. The semiconductor chip includes a plurality of embedded metal layers, a passivation layer formed above the plurality of embedded metal layers as a topmost layer of the semiconductor chip, and a plurality of bonding pads disposed on the passivation layer. A surface planar metal pattern is formed on the passivation layer and electrically connected to one of the plurality of embedded metal layers through one of the plurality of bonding pads or a via hole opened on the passivation layer. For example, the surface planar metal pattern may be connected to a power layer or a ground layer of the semiconductor chip. Therefore, the partially embedded decoupling capacitor is made up of the surface planar metal pattern as an electrode, others of the plurality of embedded metal layers as opposite electrodes, and the passivation layer sandwiched therebetween as a dielectric layer.

Abstract: A memory read/write arbitration method is disclosed. The memory read/write arbitration method, which is utilized in a memory controller for increasing row hit rate and decreasing the delay of memory access, comprises: providing a arbitrator; providing a read request fifo queue having command read requests; providing a write request fifo queue having command write requests; performing a judgment step for generating a priority, wherein the judgment step comprises: performing a first sub-judgment step to determine that a command read request of the command read requests has priority over a command write request of the command write requests, or the command write request can be forwarded to a second sub-judgment step under adaptive first-step conditions; performing the second sub-judgment step to determine the read request has priority over the command write request from the first sub-judgment step, or the command write request from the first sub-judgment has priority over the command read request.

Abstract: Methods and structures are provided for extremely flat wafer chucks, allowing close thermal contact uniformly across a semiconductor processing substrate. An upper and a lower section are tightly fit to one another with flat inner surfaces in face-to-face contact. The sections also define at least one groove therebetween. The two sections have asymmetrical thickness, but the groove defined therebetween is correspondingly asymmetrical such that the groove is centered in the assembled chuck. A heater element, such as a resistive heater, is placed within the groove with some clearance prior to assembling the upper and lower sections. After assembly and tightening, the chuck is thermally cycled above the normal operating temperature prior to secondary machining, thus assuring flatness that is maintained during high temperature operation.

Abstract: An ESD protection circuit for Mixed-Voltage I/O by using stacked NMOS transistors with substrate triggering technique is disclosed. The ESD protection circuit contains a set of stacked NMOS transistors with a first NMOS transistor and a second NMOS transistor, a parasitic lateral bipolar transistor, a substrate current generating circuit, and a parasitic substrate resistor. The drain of the first NMOS transistor connects to an I/O pad. The gate of the first NMOS transistor connects to a first working voltage. The source of the first NMOS transistor connects to the drain of the second NMOS transistor. The gate of the second NMOS transistor connects to an internal circuit. The source of the second NMOS transistor connects to a second working voltage. The collector of the parasitic lateral bipolar transistor connects to the drain of the first NMOS transistor and its emitter connects to the source of the second NMOS transistor.

Abstract: A scrubbing assembly for a wafer-cleaning device is provided. The wafer-cleaning device is provided with a base. The scrubbing assembly comprises a scrubber, a cup and an oscillator. The scrubber is disposed on the base in a manner such that it can move between a first position and a second position. The scrubber scrubs a wafer when it locates in the first position. The cup, for receiving DI water, is disposed on the base. The scrubber locates inside the cup and contacts the DI water when it locates in the second position. The oscillator is disposed at the cup, and it vibrates the DI water when the scrubber locates inside the cup and is contact with the DI water.

Abstract: A method and apparatus for an event detector using an array of passive infrared detector elements, which uses interchangeable spectral filters and lenses to permit detection of a range of event types, which normally each require individual detectors with specific spectral/optical designs.

Abstract: A multi-layered substrate having built-in capacitors is disclosed. The substrate comprises at least one high permittivity of dielectric material filled in the through holes between the power plane and the ground plane so as to form capacitors. The built in capacitors are to decouple high frequency noise due to the voltage fluctuation.

Abstract: A digital frequency comparator includes two double-edge triggered flip-flops and a combination logic. Each of the double-edge triggered flip-flops includes two D-type flip-flops and two multiplexers. The first D-type flip-flop receives a first reference clock pulse and is triggered by a data signal. The second D-type flip-flop receives the first reference clock pulse and is triggered by the reverse of the data signal. The first multiplexer provides the output of the first D-type flip-flop when the data signal is 1 and the output of the second D-type flip-flop when the data signal is 0. The second multiplexer provides the output of the first D-type flip-flop when the data signal is 0 and the output of the second D-type flip-flop when the data signal is 1. The combination logic enables an UP pulse when the data signal transmission clock is faster in frequency than the first reference clock signal.

Abstract: A method for improving adhesion of a low k dielectric to a barrier layer. A substrate covered by an insulating layer having copper interconnects is provided. A sealing layer is formed on the copper interconnects and the insulating layer. A plasma treatment is performed on the sealing layer by a reaction gas including at least one of CO2, NH3, NO2, SiH4, trimethylsilane, and tetramethylsilane. A low k dielectric layer is formed on the sealing layer.

Abstract: An apparatus is adapted for interleaving an incoming stream of data blocks, each of which has a predetermined number (N) of block units indexed consecutively from 0 to (N−1), The interleaving is accomplished at a predetermined interleaving depth (D). A first one of the block units has no delay associated therewith, and subsequent ones of the block units in a designated one of the data blocks have a delay equal to (D−1) more than an immediately preceding one of the block units in the designated one of the data blocks. The apparatus includes a data buffer configured to have a number of lines equal to (N−1), an output unit, and a control unit. Each of the lines has a size sufficient to accommodate a predetermined number of the block units. The output unit outputs one of the block units of the incoming stream directly when the delay associated therewith is equal to zero.

Abstract: A barrier control scheme controls the order dependency of items in a multiple FIFO queue structure. The barrier control scheme includes a cycle ID generator, a barrier bit/barrier ID generator and a cycle ID and barrier ID comparator. Each incoming item to the FIFOs is assigned a cycle ID. If an incoming item of a first FIFO has order dependency on items of a second FIFO, a barrier bit is set and a barrier ID is determined and generated by the barrier bit/barrier ID generator. The barrier bit and barrier ID are inserted in the first FIFO along with other fields of the incoming item. When an item is to be consumed, the cycle ID and barrier ID comparator compares its barrier ID and the cycle IDs of items in the second FIFO. The item to be consumed is blocked until all items on which the item is dependent are consumed in the second FIFO.

Abstract: Elements of a sensor system are encapsulated into a single package. The sensor elements are covered with a flexible gel coat and then inserted into a molding tool cavity. Each element may be individually coated with a gel blob, or all elements may by coated with a single gel blob. One or more retractable pins are incorporated into the molding tool and in their normal position are each in contact with the gel. A molding compound is injected into the cavity so as to encapsulate the device and gel coat. When the pins are extracted and the device ejected from the molding cavity, one or more passageways in the molding are left defined by the pins. The passageways expose the flexible gel covering the device elements to the atmosphere. For pressure sensitive elements, the gel, being flexible, transfers the local air pressure to the pressure sensitive element. For optical elements, the exposed gel is preferably removed to allow for the passage of radiation to and from the device elements.

Abstract: A current output circuit for use in a digital-to-analog converter is disclosed. The current output circuit includes a current source for providing a driving current, and a first output circuit coupled with the current source. The first output circuit includes a first metal-oxide semiconductor (MOS) transistor device having a source electrode thereof connected to the current source in series, a first voltage amplifier coupled between the source electrode and a gate electrode of the first MOS transistor device for keeping a voltage of the source electrode substantially constant, and a first controlled switch coupled between an operational voltage and the gate electrode of the first MOS transistor device for being switched ON or OFF in response to a first digital control signal, and allowing the driving current to be outputted from a drain electrode of the MOS transistor device when the first controlled switch is switched ON.