Abstract: A core logic circuit for use with a CPU and a main graphics accelerator in a computer system is provided. The core logic chip includes a host controller electrically connected to the CPU for receiving a command from the CPU; an auxiliary graphing engine electrically connected to the host controller fore receiving and processing the command; and a transmission controller electrically connected to the auxiliary graphing engine for transmitting the command processed and outputted by the auxiliary graphing engine to the main graphics accelerator to be further processed.

Abstract: An end-effector with integrated cooling features comprises heat transferring mechanisms that transfer heat energy away from the end-effector. The end-effector advantageously minimizes the cooling overhead of a processed substrate as it is transported from a process module to a low-cost storage cassette. The reduced cooling overhead of the processed substrate, as a consequence, improves substrate throughput. In the preferred embodiments, the heat transferring mechanisms include a high surface area heat sink connecting the substrate-supporting paddle with a robot arm. Cooling fins can enhance surface area and thus enhance heat dissipation from the heat sink. Cooling channels can extend through paddle and heat sink, either containing circulating fluid for carrying heat beyond the end-effector or a phase changing material in an enclosed heat pipe.

Abstract: A testing jig for semiconductor components, mainly comprising a main jig body, wherein on its bottom is provided with a retrieving head. While on the center of the bottom of the retrieving head is provided with a concave space, around which is arranged a plurality of air holes which are connected with the internal airways and also connected with the air inlet on the top of the main body. Furthermore, on the bottom of the main jig body is provided with two buffer blocks on opposite sides, which can prevent the chip on the center of the base board from being contacted with external force or foreign objects in the process of retrieving the base board during testing.

Abstract: This invention provides a metal capacitor with damascene structures. Before the thin-film capacitor is formed, the underlying interconnections, such as a first Cu wire and a second Cu wire, are fabricated with Cu by damascene processes. The thin-film capacitor is composed of a first metal layer contacting the first Cu wire, a dielectric layer and a second metal layer. A first Cu damascene structure and a second Cu damascene structure are disposed on the thin-film capacitor and the second Cu wire, respectively.

Abstract: This invention provides a metal capacitor with damascene structures. Before the thin-film capacitor is formed, the underlying interconnections, such as a first Cu wire and a second Cu wire, are fabricated with Cu by damascene processes. The thin-film capacitor composed of a first metal layer contacting the first Cu wire, a dielectric layer and a second metal layer is formed in an insulator and a stop layer. A first Cu damascene structure and a second Cu damascene structure are disposed on the thin-film capacitor and the second Cu wire, respectively.

Abstract: This invention provides a metal capacitor with damascene structures. Before the thin-film capacitor is formed, the underlying interconnections, such as a first Cu wire and a second Cu wire, are fabricated with Cu by damascene processes. The thin-film capacitor composed of a first metal layer contacting the first Cu wire, a dielectric layer and a second metal layer is formed in an insulator and a stop layer. A first Cu damascene structure and a second Cu damascene structure are disposed on the thin-film capacitor and the second Cu wire, respectively.

Abstract: A process for fabricating a dual damascene structure. First, a substrate having a dielectric layer is provided. A cap layer and a mask layer with at least one trench pattern are sequentially formed on the dielectric layer. Thereafter, a photoresist layer with at least one via pattern aligned with the trench pattern is formed overlaying the mask layer and part of the cap layer. Next, the via pattern is transferred into the cap layer and the upper half of the dielectric layer. The photoresist layer is then removed. Subsequently, the trench pattern is transferred into the cap layer and the upper half of the dielectric layer, and simultaneously the via pattern in the upper half of the dielectric layer is transferred into the lower half of the dielectric layer. Finally, the trench and the via in the dielectric layer are filled with a conductive layer.

Abstract: The present invention discloses a current feedback operational amplifier, whose input ends are connected to a first amplifier which transmits an output to the gate terminals of at least one input pair of current switches, and the source terminal of one transistor of the input pair of current switches is connected to one of the input ends. Therefore, a negative feedback loop will be established by the first amplifier and the input pair of current switches. By means of the negative feedback loop, the input impedance, offset voltage and gain error are all reduced. The input impedance of the present invention is reduced as 1/1+A times as the original one. Therefore, the aspect ratio of the transistors of the input pair of current switches is reduced.

Abstract: This invention provides a method for forming a metal capacitor in a damascene process. Before the thin-film capacitor is formed, the underlying interconnections are fabricated with Cu metal by damascene process. The lower electrode is formed in a dual damascene process, which is also used to form the dual damascene structures comprising wires and plugs. An insulator is disposed to isolate the dual damascene structures with each other. In this dual damascene process, an anti-reflection layer is used and formed on the insulator, and the anti-reflection layer is also used as a hard mask layer, a polishing stop layer and an etching stop layer. Then, another insulator and a metal layer are formed on the anti-reflection layer, and encounter a photolithography step and an etching step to obtain an upper electrode and a capacitor insulator. After forming the metal capacitor, the upper interconnections are fabricated with another dual damascene processes.

Abstract: A novel process for isolating devices on a semiconductor substrate is disclosed. An isolation layer is first formed over the semiconductor substrate and patterned into at least two isolation mesas on the substrate. Next, a blanket semiconductor layer is formed over the substrate with a thickness sufficient to cover the isolation mesas. The semiconductor layer is subjected to planarization until the isolation mesas are exposed, thus resulting in a semiconductor region between the two isolation mesas to serve as an active region for semiconductor devices.

Abstract: This invention provides a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: A storage card (1), for use together with a CD, DVD or similar device, has a rectangular shape that includes a circular segment (4) for storing information. The card has four right-angled corners (2) that are rounded and the rounding is equivalent to the circumference of the outer edge of mini-CD.

Abstract: This invention provides a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract: An image of a scene is focused onto a two dimensional array of passive infrared sensing elements mounted on and connected to an integrated circuit, and used to detect the location of events within the scene; for example, movement, change in temperature, or the emission of a gas. In this invention knowledge of the location of the event is derived from the detection of signals from one or more elements of the array, and is used to control the operation of a mechanism such that a portion of the scene including the event location is imaged onto a video imaging device operating in the visible or near infrared. Such mechanisms include a zoom lens or mirror arrangement and mechanical scanning in elevation and/or azimuth. Examples of suitable imaging devices for use with the thermal detector array include CCD camera chips and other electrically scanned silicon photovoltaic arrays. The CCD array might for example be used in a CCD camera, which is used to identify an intruder, or to read the number plate of a car.

Abstract: A dual damascene process is applied on a semiconductor substrate having a dual damascene opening with a via hole which exposes a metal wire and is surrounded by a first low-k dielectric layer, and a trench which is over the via hole and surrounded by a second low-k dielectric layer. An in-situ oxide liner, serving as a dielectric barrier layer, is formed on the sidewall of the first low-k dielectric layer and the second low-k dielectric layer. A metal barrier layer is conformally deposited on the exposed surface of the semiconductor substrate to cover the sidewall and bottom of the dual damascene opening. The dual damascene opening is filled with a conductive layer, and then the excess conductive layer outside the trench level is polished away by a CMP process.

Abstract: The present invention discloses an apparatus and method for adjusting 3D transformation applied in a 3D computer graphic processing system, using a simple and practical computing method to simulate visual effect of human's eyes to separate input video into a left video and a right video. By the focus effect of the left video and the right video, a user can feel effect of changing depth of the input video, and creating 3D effect. Additionally, the present invention provides many parameters for convenience in adjusting the video depth and location in a display plane by users.

Abstract: A three-dimensional graphics display system has a computational unit for computing the attribute values of several successive pixels at the same time for a specific graphics attribute. By time-sharing the computational unit, multiple graphics attributes can be computed using only one computational unit. The attribute values for each graphics attribute of the successive pixels are buffered in a special merge FIFO which may have a group of output data paths for sending out the attribute values of a group of pixels each computation cycle. There are multiple merge FIFOs for buffering the attribute values of the multiple graphics attributes. After the attribute values for all the desired graphics attributes for a group of pixels are available, the buffered attribute values for the group of pixels are sent out through their respective data paths. By using a pipeline architecture in the design, a high performance and low cost computation engine is provided for the three-dimensional graphics display system.

Abstract: A sensor comprising an array of detectors for e.g. infrared radiation of the type for use in security or surveillance application has means for identifying the entry of an object into a first selected area of a scene and means for generating a warning or alarm signal after a first predetermined period of time during which there is no movement of the body within the first selected area.

Abstract: A workpiece support or chuck that rapidly heats and cools a semiconductor workpiece is disclosed. A heat source and a cooling source, maintained at different temperatures, alternately communicate with the chuck. In one embodiment, the heat source and cooling source alternately provide relatively “hot” and “cold” heat transfer fluids to fluid channels within the workpiece chuck. Accordingly, a semiconductor workpiece in contact with the chuck rapidly heats to the temperature of the hot fluid, or rapidly cools to the temperature of the cold fluid, depending upon which fluid flowing through the chuck. In another embodiment, the heat source comprises a movable resistive heating block at a first temperature that is placed in contact with the chuck during heating, and is removed from the chuck while colder heat transfer fluid circulates within the chuck. Optionally, inert fluid can be provided to purge heat transfer fluid from the chuck channels between heating and cooling steps.

Abstract: A multi-shifting shift register is adapted for outputting a selected address signal to a memory unit, and includes a control circuit for outputting a number (i) of shift signals and a timing pulse signal. One of the shift signals is at an enabled state and the other ones of the shift signals are at a disabled state during each cycle of the timing pulse signal. A multi-shifting circuit includes a number (N), which is larger than the number (i), of cascaded register units, each of which has a flip-flop that has an input end, and an output end for generating an address signal, and a selector that has the number (i) of select inputs for receiving the number (i) of the shift signals respectively from the control circuit, the number (i) of address signal inputs, and an output. The output end of the flip-flop is connected to a first one of the address signal inputs of the selector.