Patents Assigned to Intel Corporation
  • STACKED VIAS WITH BOTTOM PORTIONS FORMED USING SELECTIVE GROWTH
    Publication number: 20250125255
    Abstract: Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using selective growth, e.g., assisted by a self-assembled monolayer (SAM) material.
    Type: Application
    Filed: December 5, 2024
    Publication date: April 17, 2025
    Applicant: Intel Corporation
    Inventors: Andy Chih-Hung Wei, Guillaume Bouche
  • NETWORK ALLOCATION VECTOR TIMEOUT FOR ULTRA HIGH RELIABILITY INITIAL CONTROL FRAME EXCHANGE
    Publication number: 20250125839
    Abstract: This disclosure describes systems, methods, and devices related to NAV timeout. A device may transmit, during a transmission opportunity (TxOP), an initial control frame (ICF) trigger frame including user information fields identifying one or more target stations (STAs). The device may receive from the one or more target STAs, an initial control response (ICR) frame, wherein the ICR frame includes feedback information and padding. The device may calculate a network allocation vector (NAV) timeout period based on a transmission time of a maximum-sized ICR frame at a lowest transmission rate. The device may adjust NAV settings based on the NAV timeout period.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Applicant: Intel Corporation
    Inventors: Laurent CARIOU, Thomas J. KENNEY
  • Generation of three-dimensional representation of object surface from structured point-cloud
    Patent number: 12275158
    Abstract: A system for generating a three-dimensional (3D) representation of a surface of an object. The system includes a point cloud processor and an object surface representation processor. The point cloud processor is to generate a structured point cloud of the object based on sensor data received from a sensor. The object surface representation processor is to: identify surface nodes in the structured point cloud; and link each surface node with any of its active neighbors to generate a surface net, wherein the linking comprises simultaneously establishing a forward-connectivity-link for a respective surface node to an active neighbor and a reverse-connectivity-link for the active neighbor to the respective surface node.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventor: David Gonzalez Aguirre
  • Setting default physical downlink shared channel (PDSCH) beams
    Patent number: 12279247
    Abstract: In accordance with various embodiments herein, for single downlink control information (DCI) and/or multi-DCI multi-transmission-reception point (TRP) transmission, a default physical downlink shared channel (PDSCH) beam is determined based on the lowest indexed control resource set (CORESET) within the set of monitored CORESETs in the latest slot with the same value of CORESETPoolIndex. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Bishwarup Mondal, Alexei Davydov
  • Cryptographic computing in multitenant environments
    Patent number: 12277234
    Abstract: A processor, a system, a machine readable medium, and a method.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: David M. Durham, Michael D. LeMay, Salmin Sultana, Karanvir S. Grewal, Michael E. Kounavis, Sergej Deutsch, Andrew James Weiler, Abhishek Basak, Dan Baum, Santosh Ghosh
  • Apparatus, system, and method of functional safety
    Patent number: 12276963
    Abstract: For example, an apparatus may include a motherboard including a functional processing core configured to perform a functionality having a Functional Safety (FuSa) level; a FuSa transceiver configured to communicate with an external safety-island processor, which is external to the motherboard; and a FuSa controller configured to establish a FuSa connection with the external safety-island processor according to the FuSa level, to send FuSa information corresponding to the functionality of the functional processing core to the external safety-island processor via the FuSa transceiver, and to control one or more FuSa operations of the functional processing core based on one or more control messages received from the external safety-island processor via the FuSa transceiver.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: April 15, 2025
    Assignee: INTEL CORPORATION
    Inventors: Darshan Raj, Michael Schmidt, Serdar Gueltekin
  • TMD inverted nanowire integration
    Patent number: 12278289
    Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.
    Type: Grant
    Filed: January 16, 2024
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Kevin P. O'Brien, Carl Naylor, Chelsey Dorow, Kirby Maxey, Tanay Gosavi, Ashish Verma Penumatcha, Shriram Shivaraman, Chia-Ching Lin, Sudarat Lee, Uygar E. Avci
  • Computing devices with secure boot operations
    Patent number: 12277228
    Abstract: Disclosed herein are embodiments related to security in cloudlet environments. In some embodiments, for example, a computing device (e.g., a cloudlet) may include: a trusted execution environment; a Basic Input/Output System (BIOS) to request a Key Encryption Key (KEK) from the trusted execution environment; and a Self-Encrypting Storage (SES) associated with the KEK; wherein the trusted execution environment is to verify the BIOS and provide the KEK to the BIOS subsequent to verification of the BIOS, and the BIOS is to provide the KEK to the SES to unlock the SES for access by the trusted execution environment.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Yeluri Raghuram, Susanne M. Balle, Nigel Thomas Cook, Kapil Sood
  • Patterned bolster plate and composite back plate for semiconductor chip LGA package and cooling assembly retention
    Patent number: 12279395
    Abstract: An apparatus is described. The apparatus includes a back plate, where, an electronic circuit board is to be placed between the back plate and a thermal cooling mass for a semiconductor chip package. The back plate includes a first material and a second material. The first material has greater stiffness than the second material. The back plate further includes at least one of: a third material having greater stiffness than the second material; re-enforcement wires composed of the first material; a plug composed of the second material that is inserted into a first cavity in the first material, a stud inserted into a second cavity in the plug. An improved bolster plate having inner support arms has also been described.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Phil Geng, Ralph V. Miele, David Shia, Jeffory L. Smalley, Eric W. Buddrius, Sean T. Sivapalan, Olaotan Elenitoba-Johnson, Mengqi Liu
  • Ultra-low latency inter-satellite communication links
    Patent number: 12278690
    Abstract: Various approaches for the deployment and coordination of inter-satellite communication pathways, defined for use with a satellite non-terrestrial network, are discussed. Among other examples, such inter-satellite communication pathways may be identified, reserved, allocated, and used for ultra-low-latency communication purposes.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Stephen T. Palermo, Valerie J. Parker, Udayan Mukherjee, Rajesh Gadiyar, Jason K. Smith
  • Defect detection using thermal laser stimulation and atomic force microscopy
    Patent number: 12276696
    Abstract: The present disclosure is directed to an inspection tool having an integrated optical laser unit and atomic force probe unit with a detector unit. The inspection tool further includes a processor unit that is coupled to the optical laser unit and the atomic force probe unit and performs a fault location analysis for a device under test. In addition, the present disclosure to methods for inspecting a device under test for defects using an inspection tool having an integrated optical laser unit and atomic force probe unit that includes a detector unit.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Huei Hao Yap, Gavin Corcoran, Jungwon Kim, Seung Hwan Lee, Mark Gruidl, Karthik Kalaiazhagan, Youren Xu
  • Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)
    Patent number: 12277060
    Abstract: Methods and example implementations described herein are generally directed to the addition of networks-on-chip (NoC) to FPGAs to customize traffic and optimize performance. An aspect of the present application relates to a Field-Programmable Gate-Array (FPGA) system. The FPGA system can include an FPGA having one or more lookup tables (LUTs) and wires, and a Network-on-Chip (NoC) having a hardened network topology configured to provide connectivity at a higher frequency that the FPGA.
    Type: Grant
    Filed: May 29, 2021
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventor: Sailesh Kumar
  • Hybrid manufacturing for integrated circuit devices and assemblies
    Patent number: 12278229
    Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Abhishek A. Sharma, Mauro J. Kobrinsky, Doug B. Ingerly
  • Technologies for repair of memory with access lines
    Patent number: 12277985
    Abstract: Techniques for repair of a memory die are disclosed. In the illustrative embodiment, a faulty wordline (or bitline) can be remapped to a redundant wordline on the same layer by entering the address of the faulty wordline in a repair table for the layer. If there are more faulty wordlines on a layer than redundant wordlines available on the layer, the faulty wordlines can be remapped to redundant wordlines on a different layer, and the address of the faulty wordline can be placed in a repair table for the different layer. When a memory operation is received, the wordline address for the memory operation is checked against the repair tables to check if it remapped.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: William K. Waller, Dhruval J. Patel, Xiannan Di
  • High speed interconnect symbol stream forward error-correction
    Patent number: 12278701
    Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.
    Type: Grant
    Filed: March 22, 2024
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Nausheen Ansari, Ziv Kabiry, Gal Yedidia
  • Switchable antenna system
    Patent number: 12278659
    Abstract: A wireless computing device may include an internal antenna, a radio frequency (RF) transmission path that is switchably connectable to the internal antenna, a Universal Serial Bus (USB) connector configured to connect to an external antenna, a detector configured to detect if an external antenna is connected to the USB connector, and an antenna selector configured to (1) connect the internal antenna into the RF transmission path if the detector detects that no external antenna is connected to the USB connector and (2) disconnect the internal antenna from the RF transmission path and connect the external antenna into the RF transmission path if the detector detects that the external antenna is connected to the USB connector, thereby improving the wireless transmission/reception performance of the internal wireless module of the wireless computing device.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Smit Kapila, Jayprakash Thakur, Santosh Gangal
  • Apparatuses, methods, and systems for instructions to convert 16-bit floating-point formats
    Patent number: 12277419
    Abstract: Systems, methods, and apparatuses relating to instructions to convert 16-bit floating-point formats are described. In one embodiment, a processor includes fetch circuitry to fetch a single instruction having fields to specify an opcode and locations of a source vector comprising N plurality of 16-bit half-precision floating-point elements, and a destination vector to store N plurality of 16-bit bfloat floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the source vector from 16-bit half-precision floating-point format to 16-bit bfloat floating-point format and store each converted element into a corresponding location of the destination vector, decode circuitry to decode the fetched single instruction into a decoded single instruction, and the execution circuitry to respond to the decoded single instruction as specified by the opcode.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Alexander F. Heinecke, Robert Valentine, Mark J. Charney, Menachem Adelman, Christopher J. Hughes, Evangelos Georganas, Zeev Sperber, Amit Gradstein, Simon Rubanovich
  • Multimodal intent recognition for telepresence robots
    Patent number: 12275156
    Abstract: Disclosed herein are systems and methods for controlling a telepresence robot, sometimes referred to as a receiver. The systems and methods may include obtaining environmental data associated with the receiver and/or an operator of the telepresence robot, sometimes referred to as a sender. A model defining a human intent may be received and an intent of a human proximate the receiver and or the sender may be determined using the model. A first signal may be transmitted to the receiver. The first signal may be operative to cause the receiver to alter a first behavior based on the intent of the human and/or the sender.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Sangeeta Manepalli, Siew Wen Chin
  • Calibration for DTC fractional frequency synthesis
    Patent number: 12278643
    Abstract: A digital-to-time converter (DTC)-based open loop frequency synthesis and calibration circuit may be used to provide a precise clock signal. The DTC calibration circuit may include a DTC to generate a DTC clock signal based on a received input clock frequency and a received initial digital input code, a phase-lock loop (PLL) to generate a PLL clock signal based on a received PLL input, a binary phase-detector (PD) to generate a PD output based on a comparison between the DTC clock signal and the PLL clock signal, a plurality of calibration bins to generate a signed accumulated PD portion based on the PD output, and an adder to generate a calibrated DTC input code based on a combination of the signed accumulated PD portion and a subsequent digital input code, where the DTC generates a calibrated clock signal based on the calibrated DTC input code.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Somnath Kundu, Stefano Pellerano, Brent R. Carlton
  • Gate contact structure over active gate and method to fabricate same
    Patent number: 12278144
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: April 15, 2025
    Assignee: Intel Corporation
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani