Abstract: Embodiments for orchestrating execution of workloads on a distributed computing infrastructure are disclosed herein. In one example, environment data is received for compute devices in a distributed computing infrastructure. The environment data is indicative of an operating environment of the respective compute devices and a physical environment of the respective locations of the compute devices. Future operating conditions of the compute devices are predicted based on the environment data, and workloads are orchestrated for execution on the distributed computing infrastructure based on the predicted future operating conditions.

Abstract: Methods, systems, and articles are described herein related to video coding. The method comprises receiving compressed image data of video frames including a block of image data of at least one of the frames. The method also comprises receiving first partition data to be used to decode the compressed image data and indicating a partition in the block. This method comprises detecting whether or not the block has an illegal block partition. Also, the method comprises generating second partition data to indicate the illegal block partition of the block is to be ignored. Further, the method includes decoding the block at least according to the second partition data.

Abstract: Technologies for cryptographic separation of MMIO operations with an accelerator device include a computing device having a processor and an accelerator. The processor establishes a trusted execution environment. The accelerator determines, based on a target memory address, a first memory address range associated with the memory-mapped I/O transaction, generates a second authentication tag using a first cryptographic key from a set of cryptographic keys, wherein the first key is uniquely associated with the first memory address range. An accelerator validator determines whether the first authentication tag matches the second authentication tag, and a memory mapper commits the memory-mapped I/O transaction in response to a determination that the first authentication tag matches the second authentication tag. Other embodiments are described and claimed.

Abstract: Described herein is a technique and associated tool for automatic program code optimization for high-level synthesis. The tool can efficiently explore multiple representations of an input program using e-graph rewriting and determine an HLS-efficient representation of program code for input into high-level synthesis tools.

Abstract: Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: For example, a wireless communication device may be configured to determine an expected interference-based value corresponding to an Uplink (UL) transmission from a wireless communication station (STA) in a Trigger-Based (TB) Multi-User (MU) UL transmission to be communicated from a plurality of STAs to the wireless communication device; to determine one or more transmit (Tx) configuration parameters for the STA based on the expected interference-based value corresponding to the UL transmission from the STA; and to transmit a trigger frame to trigger the TB MU UL transmission, the trigger frame including the one or more Tx configuration parameters to configure the UL transmission from the STA.

Abstract: A graph neural network (GNN) model is used in a scheduling process for compiling a deep neural network (DNN). The DNN, and parameter options for scheduling the DNN, are represented as a graph, and the GNN predicts a set of parameters that is expected to have a low cost. Using the GNN-based model, a compiler can produce a schedule for compiling the DNN in a relatively short and predictable amount of time, even for DNNs with many layers and/or many parameter options. For example, the GNN-based model reduces the overhead of exploring every parameter combination and does not exclude combinations from consideration like prior heuristic-based approaches.

Abstract: Embodiments are generally directed to an adaptive deformable kernel prediction network for image de-noising. An embodiment of a method for de-noising an image by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel values for the pixel; generating a plurality of offsets for the pixel respectively corresponding to the plurality of kernel values, each of the plurality of offsets to indicate a deviation from a pixel position of the pixel; determining a plurality of deviated pixel positions based on the pixel position of the pixel and the plurality of offsets; and filtering the pixel with the convolutional kernel and pixel values of the plurality of deviated pixel positions to obtain a de-noised pixel.

Abstract: For example, an Access Point (AP) may be configured to process network slicing information including slice identification information and Service Level Agreement (SLA) information, wherein the slice identification information is to identify one or more Quality of Service (QoS) network slices. For example, the AP may be configured to determine a configuration of one or more radio resource allocations to be assigned to the one or more QoS network slices, and to transmit a network slicing advertisement including network slicing assignment information to indicate an assignment of the one or more radio resource allocations to the one or more QoS network slices.

Abstract: Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.

Abstract: Processor trace systems and methods are described. For example, one embodiment comprises executing instrumented code by a compiler, the instrumented code including at least one call to un-instrumented code. The compiler can determine the at least one call to un-instrumented code is a next call to be executed. A resume tracing instruction can be inserted into the instrumented code prior to the at least one call to the un-instrumented code. The resume tracing instruction can be executed to selectively add processor tracing to the at least one call to the un-instrumented code, and the at least one call to the un-instrumented code can be executed.

Abstract: In one embodiment, an apparatus comprises circuitry, wherein the circuitry is configured to: receive, via a communications network, context information for a first set of one or more edge devices, wherein the context information identifies an operating environment of the first set of edge devices based on information from one or more sensors; receive, via the communications network, workload information for a second set of one or more edge devices; determine workload assignments for the first set of edge devices based on the context information for the first set of edge devices and based on the workload information for the second set of edge devices; and transmit, via the communications network, the workload assignments to the first set of edge devices.

Abstract: An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a sandwich plate construction heatsink. The sandwich plate construction heatsink can include a cold plate, one or more heat pipes over the cold plate, and a top plate over the one or more heat pipes. The cold plate can include a channel to accommodate the one or more heat pipes and/or the top plate can include a channel to accommodate the one or more heat pipes. The cold plate can be over a heat source in the electronic device.

Abstract: A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.

Abstract: Various embodiments generally may relate to Load Balancing Optimization (LBO) and Mobility Robustness Optimization (MRO). Some embodiments of this disclosure are directed to the following 5G SON solutions: use cases and requirements for the management of distributed LBO and centralized LBO; procedures for the management of distributed LBO and centralized LBO; and management services and information needed to support the management of distributed LBO and centralized LBO.

Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

Abstract: An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.