Abstract: A base station (BS) circuitry, configured to adapt operation of a user equipment (UE) between a stand-alone operation mode and a mobile network operator (MNO) assisted operation mode, includes: a first interface connectable to an MNO network; a second interface connectable to the UE; and a BS controller, configured to: transmit a first register message via the first interface to the MNO network, wherein the first register message indicates a request to operate the UE in at least one licensed frequency band of the MNO network, and signal a hand-over via the second interface to the UE, wherein the hand-over indicates a transition from operating the UE in at least one frequency band of the stand-alone operation mode to operating the UE in the at least one licensed frequency band of the MNO assisted operation mode.

Abstract: Systems and methods for tone mapping of high dynamic range (HDR) images for high-quality deep learning based processing are disclosed. In one embodiment, a graphics processor includes a media pipeline to generate media requests for processing images and an execution unit to receive media requests from the media pipeline. The execution unit is configured to compute an auto-exposure scale for an image to effectively tone map the image, to scale the image with the computed auto-exposure scale, and to apply a tone mapping operator including a log function to the image and scaling the log function to generate a tone mapped image.

Abstract: A controller including a processor configured to obtain a message from a task performing agent of a group of task performing agents allocated to a plurality of tasks, wherein the message comprises information about one or more assessments of the task performing agent, wherein the one or more assessments are based on a sensing process performed by one or more sensors of the task performing agent, wherein the task performing agent is an autonomous machine or a human agent equipped with sensors; and allocate a task of the plurality of tasks to the task performing agent, based on the information and based on whether the task performing agent is an autonomous machine or a human agent.

Abstract: Electronic devices with moveable display screens are described herein. An example electronic device includes a lid having a first display screen and a base. The lid is moveably coupled to the base. The base includes a housing having a top side and a bottom side, a physical keyboard to be accessed on the top side of the housing, and a second display screen moveable between a first position in which the keyboard is exposed and a second position in which the second display screen covers the keyboard.

Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described.

Abstract: Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.

Abstract: In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.

Abstract: Examples include techniques for near data acceleration for a multi-core architecture. A near data processor included in a memory controller of a processor may access data maintained in a memory device coupled with the near data processor via one or more memory channels responsive to a work request to execute a kernel, an application or a loop routine using the accessed data to generate values. The near data processor provides an indication to the requestor of the work request that values have been generated.

Abstract: Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.

Abstract: Embodiments are directed to protection of communications between a trusted execution environment and a hardware accelerator utilizing enhanced end-to-end encryption and inter-context security. An embodiment of an apparatus includes one or more processors having one or more trusted execution environments (TEEs) including a first TEE to include a first trusted application; an interface with a hardware accelerator, the hardware accelerator including trusted embedded software or firmware; and a computer memory to store an untrusted kernel mode driver for the hardware accelerator, the one or more processors to establish an encrypted tunnel between the first trusted application in the first TEE and the trusted software or firmware, generate a call for a first command from the first trusted application, generate an integrity tag for the first command, and transfer command parameters for the first command and the integrity tag to the kernel mode driver to generate the first command.

Abstract: In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.

Abstract: A pedestrian route can be segmented into at least one pedestrian walking segment using location information of transportation resources. An estimated transit time for the pedestrian route can be determined as a function of an estimated transit time of the at least one pedestrian walking segment, an estimated wait time for the transportation resource to arrive at the user determined using received status real-time location and movement information of the transportation resource and the determined estimated transit time for the at least one pedestrian walking segment, and an estimated transit time for the transportation resource to transport the user.

Abstract: Techniques for operating on an indirect memory access instruction, where the instruction accesses a memory location via at least one indirect address. A pipeline processes the instruction and a memory operation engine generates a first access to the at least one indirect address and a second access to a target address determined by the at least one indirect address. A cache memory used with the pipeline and the memory operation engine caches pointers. In response to a cache hit when executing the indirect memory access instruction, operations dereference a pointer to obtain the at least one indirect address, not set a cache bit, and return data for the instruction without storing the data in the cache memory; and in response to a cache miss, operations set the cache bit, obtain, and store a cache line for a missed pointer, and return data without storing the data in the cache memory.

Abstract: Protrusions of socket bodies having metal are disclosed. An example apparatus comprises a socket body, the socket body including a plastic material, an array of contacts distributed across a surface of the socket body, and a protrusion extending away from the surface of the socket body, the protrusion to facilitate alignment of an IC package with the array of contacts, the protrusion including metal.

Abstract: Methods, systems, articles of manufacture and apparatus are disclosed to generate dynamic computing resource schedules. An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to determine a first schedule policy based on (a) an interval parameter and (b) an energy budget parameter, the first schedule policy to include a first instantiation window. The example instructions further determine performance metrics of a target processor circuit based on instantiating a workload with the first schedule policy, and generate a second schedule policy based on the performance metrics of the target processor circuit, the second schedule policy to include a second instantiation window, the second instantiation window including a modification relative to the first instantiation window.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing for integrating photonic and electronic components, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by bonding at least two IC structures fabricated using different manufacturers, materials, or manufacturing techniques. Before bonding, at least one IC structure may include photonic components such as optical waveguides, electro-optic modulators, and monolithically integrated lenses, and at least one may include electronic components such as electrically conductive interconnects, transistors, and resistors. One or more additional electronic and/or photonic components may be provided in one or more of these IC structures after bonding. For example, an interconnect implemented as an electrically conductive via or a waveguide implemented as a dielectric via may be provided after bonding to extend through one or more of the bonded IC structures.

Abstract: Methods and apparatus for semiconductor die fault analysis are disclosed. An example apparatus comprises interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to identify a location of a reference feature on a semiconductor die within a first image of the semiconductor die, the first image containing a region of interest on the semiconductor die adjacent to the reference feature, transform a baseline pattern of the semiconductor die to align a location of a baseline feature in the baseline pattern with the location of the reference feature in the first image, and determine a location of the region of interest in the first image based on the transformed baseline pattern.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to prevent attacks on software. An example non-transitory machine readable storage medium comprising instructions to cause programmable circuitry to at least: insert a plurality of code blocks into an input code; insert replacement manager instructions into the input code, the replacement manager instructions to, when executed: determine a subset of the plurality of code blocks; and insert the subset of the plurality of code blocks into memory for execution during execution of the input code.

Abstract: Techniques and mechanisms for a micro-LED (or “uLED”) device to facilitate communication of an optical signal which is propagated via a transparent substrate structure. In an embodiment, one or more recess structures are formed in a side of a transparent substrate structure, such as a glass core of a package substrate. A uLED structure extends partially through the transparent substrate structure in a first recess structure, and is oriented to transmit or receive an optical signal via the transparent substrate. In another embodiment, the uLED structure is coupled to integrated circuitry which provides functionality to operate the uLED structure, at different times, in either one of an optical signal receiver mode or an optical signal transmitter mode.

Abstract: Techniques for supporting variable channel bandwidths in a wireless communications network are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a communications management module, and the communications management module may be operable by the processor circuit to determine a channel bandwidth for communication over a channel of a wireless network, transmit a beamforming initiation message comprising a channel bandwidth parameter indicating the determined channel bandwidth, receive a beamforming initiation confirmation message confirming the channel bandwidth parameter, perform a beamforming training sequence to determine one or more beamforming parameters, and transmit one or more messages over the channel according to the determined channel bandwidth and the one or more beamforming parameters. Other embodiments are described and claimed.