Abstract: Provided herein are segmented digital to analog converters (DACs), methods for use therewith, and systems that include one or more such DACs. According to an embodiment, a DAC includes a plurality of sub-DACs, a DAC input adapted to receive a multi-bit digital input and a DAC output adapted to output an analog output current in response to and indicative of the digital input. Each sub-DAC is adapted to receive a separate reference current that specifies a transfer function of the sub-DAC. A magnitude of the reference current provided to each sub-DAC is separately programmable to thereby separately control a gain of each sub-DAC.

Abstract: In accordance with an embodiment, a proximity sensor includes a driver, a photodiode (PD), an analog-to-digital converter (ADC) with analog-to-digital-to-analog (ADA) feedback, and a controller. The driver is adapted to selectively drive a light source. The photodiode (PD) is adapted to produce a photodiode current signal (Idiode) indicative of an intensity of light detected by the PD, where the light detected by the PD can include ambient light and/or light transmitted by the light source that was reflected off an object proximate the PD. The controller is adapted to control the driver and the ADC with ADA feedback. A digital output of the ADC with ADA feedback is indicative of a proximity of an object to the PD with at least a majority of the ambient light detected by the PD rejected.

Abstract: An adaptive pulse positioning system for a voltage converter including an adjustable ramp generator, a pulse generator circuit, and a sense and adjust circuit. The adjustable ramp generator has an adjust input and provides a periodic ramp voltage having an adjustable magnitude based on an adjust signal provided to the adjust input. The pulse generator circuit receives the ramp voltage and generates a pulse signal with control pulses for controlling the output voltage of the voltage controller based on the ramp voltage. The sense and adjust circuit senses an output load transient and provides the adjust signal to the adjust input of the ramp generator to adaptively shift the pulse signal in time in response to the output load transient without adding pulses to the pulse signal.

Abstract: A method of operating a synchronous power converter detects when at least one of an upper power switch and a lower power switch of the converter transition to an off state during a dead-time transition interval between the upper power switch and the lower power switch. The method generates a first comparison signal, indicative of a voltage level at a phase node of the converter, in a dead-time adjustment circuit coupled to the converter. The method further detects a body diode conduction level of at least one of the upper and lower power switches in the off state using at least a second comparison signal generated in the dead-time adjustment circuit and adjusts the dead-time transition interval between the upper power switch and the lower power switch using at least one current source from the dead-time adjustment circuit to reduce the dead-time transition interval to a desired dead-time interval.

Abstract: A technique for improving the operation of a Time Interleaved Analog to Digital Converter (TIADC) by suppressing updates and/or correction to updates of an interleave mismatch errors estimator when one or more predetermined conditions

Abstract: A technique that randomizes a sample window over which one or more interleave mismatch corrections are made to a time interleaved analog to digital converter (TIADC).

Abstract: Circuits, methods, and apparatus that provide voltage references having a temperature independent output voltage that is less then the bandgap of silicon. The temperature coefficient and absolute voltage can be independently adjusted. One example generates two voltages, the first of which is proportional-to-absolute temperature and the second of which is complementary-to-absolute temperature. These voltages are placed across a first resistor. The first resistor is further connected to a second resistor to form a resistor divider. The resistor divider provides a reduced voltage that is below that bandgap of silicon. The temperature coefficient of the reference voltage provided by the resistor divider can be set by adjusting the first resistor. The absolute voltage provided can be set by adjusting the second resistor.

Abstract: A bandgap voltage reference circuit includes a first circuit portion and a second circuit portion. The first circuit portion generates a voltage complimentary to absolute temperature (VCTAT). The second circuit portion generates a voltage proportional to absolute temperature (VPTAT) that is added to the VCTAT to produce a bandgap voltage reference output. The first circuit portion includes a plurality of delta base-emitter voltage (VBE) generators, connected as a plurality of stacks of delta VBE generators. Each delta VBE generator can include a pair of transistors that operate at different current densities and thereby generate a difference in base-emitter voltages (?VBE). The plurality of delta VBE generators within each stack are connected to one another, and the plurality of stacks of delta VBE generators are connected to one another, such that the ?VBEs generated by the plurality of delta VBE generators are arithmetically added to produce the VPTAT.

Abstract: Provided herein are amplifiers including negative capacitance circuits for reducing distortion resulting from a gate-source (or base-emitter) capacitance of output stages of such amplifiers. Such a negative capacitance circuit is connected in parallel with the gate-source (or base-emitter) capacitance of the output stage to shunt the gate-source (or base-emitter) capacitance and thereby reduce distortion. Also provided herein are methods for use with amplifiers including an output stage, including connecting a negative capacitance circuit in parallel with a base-emitter capacitance of the output stage.

Abstract: A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal, and a synchronous output switch having a phase node there between controlled by the gate driver, and regulator input current measurement circuitry. The regulator input current measurement circuitry comprises a circuit operable for providing a signal representative of at least one phase node timing parameter, a sensing circuit operable for sensing inductor or output current provided by the regulator, and a calculation circuit coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current.

Abstract: A voltage regulator system comprises circuitry for generating a regulated output voltage responsive to an input voltage and switching control signals. A voltage divider is connected to an output node of the circuitry to provide a way to monitor the output voltage. A voltage regulator controller generates the switching control signals responsive to the monitored output voltage and a reference voltage. A compensation network is associated with the voltage regulator controller. The voltage regulator controller further controls the circuitry for regulating an output current pulse for the regulated output voltage responsive to an indication that the monitored output voltage is below a reference voltage in the no-load condition without interaction with the loop compensation network.

Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

Abstract: A pulse control system for a multiphase regulator including an error amplifier, a multiphase generator, and an adaptive controller. The error amplifier provides an error signal indicative of output voltage error. The multiphase generator develops modulation pulses for phases based on the error signal. The adaptive controller is responsive to a load indication signal and redirects at least one modulation pulse from a first of phase to a second phase. The load indication signal may be received from a microprocessor indicating a low power mode. The adaptive controller provides a smooth and efficient transition to low load conditions by dropping operation of one or more phases and redirecting modulation pulses to the remaining one or more phases, and reduced phases improve power efficiency for the low load conditions.

Abstract: A multi-phase voltage regulator comprises a plurality of DC/DC voltage regulators. Each of the DC/DC voltage regulators is associated with a particular phase of the multi-phase regulator. Each of the regulators comprises a first switching transistor connected between an input voltage node and a phase node responsive to switching control signals. A second switching transistor is connected between the phase node and a ground node and is responsive to the switching control signals. An inductor is connected between the phase node and an output voltage node. Control logic generates the switching control signals responsive to a pulse control signal. PFM/PWM transition logic generates the pulse control signal. The pulse control signal transitions between a PWM signal and a PFM signal responsive to an error voltage, a feedback voltage from the output voltage node and an inductor current through the inductor. An error amplifier generates the error voltage responsive to the feedback voltage and a reference voltage.

Abstract: A DC-DC converter includes a chip including an error amplifier and a pulse width modulator (PWM) having an input connected to an output of the error amplifier, and an inductor driven by said PWM in series with an output node (VOUT) of the converter, wherein a load current flows through the inductor. VOUT is fed back through a network including a feedback resistor (RFB) to an inverting input of the error amplifier. A circuit for sensing the load current includes a first operational amplifier, a sense resistor on the chip having resistance RSENSE coupled to an inverting input of the first amplifier; wherein a sense current related to the load current flows through the sense resistor, a dependent current source provides an output current to supply the sense current. A reference resistor is disposed on the chip having a resistance RREFERENCE which is a fixed multiple of RSENSE. A set resistor is provided having a resistance RSET.

Abstract: A sigma delta converter system and method includes a multi bit quantizer circuit coupled to an output of the converter. A single bit analog-to-digital converter circuit is contained in a feedback path of the converter. The converter includes a feed forward path operable to multiply an input voltage by a feed forward coefficient having a value that is a function of a gain control input signal. The gain control input signal can have a value that is a function of the output of the multi bit quantizer.

Abstract: Provided herein are circuits, systems and methods that monitor for way out of balance (WOB) conditions within a multi-phase DC-DC converter, and adjust a balance between currents through channels of the DC-DC converter, in dependence on detected WOB conditions.

Abstract: An apparatus comprises a synchronous converter for providing a regulated output voltage responsive to an input voltage, a control PWM signal to a control switch of the synchronous converter and a synchronous PWM signal to a synchronous switch of the synchronous converter. A first circuit generates the control PWM signal and the synchronous PWM signal responsive to a PWM control signal. The first circuit limits a maximum duty cycle of the synchronous PWM signal to a predetermined level.

Abstract: A junction barrier Schottky diode has an N-type well having a surface and a first peak impurity concentration; a P-type anode region in the surface of the well, and having a second peak impurity concentration; an N-type cathode contact region in the surface of the well and laterally spaced from a first wall of the anode region, and having a third peak impurity concentration; and a first N-type region in the surface of the well and laterally spaced from a second wall of the anode region, and having a fourth impurity concentration. The center of the spaced region between the first N-type region and the second wall of the anode region has a fifth peak impurity concentration. An ohmic contact is made to the anode region and cathode contact region, and a Schottky contact is made to the first N-type region. The first and fifth peak impurity concentrations are less than the fourth peak impurity concentration, and the fourth peak impurity concentration is less that the second and third peak impurity concentrations.

Abstract: Provided herein are circuits, systems and methods that monitor for a fault within a multi-phase DC-DC converter. This can include monitoring the channels of the DC-DC converter for way out of balance (WOB) conditions, and monitoring for a component fault in dependence on detected WOB conditions. A fault can be detected if, during a predetermined period of time, one of the WOB conditions occurs at least a specified amount of times more than another one of the WOB conditions. The DC-DC converter and/or another circuit can be shut-down in response to a fault being detected. Additionally, or alternatively, a component fault detection signal can be output in response to a fault being detected.