Patents Assigned to Intersil
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Patent number: 7825429Abstract: A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached.Type: GrantFiled: January 14, 2010Date of Patent: November 2, 2010Assignee: Intersil Americas Inc.Inventor: James E. Vinson
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Publication number: 20100270995Abstract: A controller integrated circuit for a switched mode regulator which converts an input voltage to an output voltage. The controller includes a phase pin, a modulation circuit and a filter. The modulation circuit is configured to regulate the output voltage using the input voltage and output voltage level information. The filter has an input coupled to the phase pin and an output providing the output voltage level information which approximates the output voltage based on phase pin voltage. Various filters are contemplated, including passive and active low pass filters and the like. A regulator using such a controller is disclosed. A method of determining a voltage level of an output voltage includes receiving a phase voltage from a phase pin coupled to the phase node, and filtering the phase voltage to provide an output sense voltage having a voltage level approximating the voltage level of the output voltage.Type: ApplicationFiled: February 4, 2010Publication date: October 28, 2010Applicant: INTERSIL AMERICAS INC.Inventors: Steven P. Laur, Rhys S.A. Philbrick
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Publication number: 20100264895Abstract: An embodiment of a power-supply controller includes a signal combiner and a control circuit. The signal combiner is operable to generate a combined feedback signal from sense and output feedback signals that are respectively derived from a sense signal and a regulated output signal, and the signal combiner is operable to receive the sense signal from a sense circuit that is operable to generate the sense signal while a current is flowing through an inductor and while a switch that is disposed between the inductor and an input voltage has a first state. The sense signal generated by the sense circuit is related to the current, and the switch and the inductor are operable to generate the regulated output signal. The control circuit is coupled to the signal combiner and is operable to cause the switch to have a second state for a predetermined time in response to the combined feedback signal having a predetermined relationship to a reference signal.Type: ApplicationFiled: June 29, 2010Publication date: October 21, 2010Applicant: INTERSIL AMERICAS INC.Inventors: Da Feng Weng, Jinrong Qian, Tamas Szepesi
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Patent number: 7816985Abstract: Systems and methods implemented in a switching amplifier for providing consistent, matching switching between top and bottom switching devices in a switching amplifier. One embodiment includes a half-bridge circuit output stage, a driver stage and a transformer. The driver stage, which drives the switches of the output stage, is very fast, has a low propagation delay, and has minimal input capacitance. The transformer drives the drive paths from the transformer inputs to the switches. The transformer avoids resonances within the audio band and at the amplifier switching frequencies, has low and spread free leakage inductance, has enough magnetizing inductance to keep transformer currents low in proportion to the total driver stage current drain, has low core losses at the switching frequency, has minimal inductance change and operates well below its saturation point. The amplifier stage provides a substantially constant amplitude drive signal to the output power switching devices.Type: GrantFiled: November 13, 2008Date of Patent: October 19, 2010Assignee: Intersil Americas Inc.Inventors: Brian E Attwood, Wilson E. Taylor, Larry E. Hand
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Publication number: 20100258710Abstract: An optical sensor device, according to an embodiment of the present invention, includes a light source and a light detector. The light source includes one or more light emitting elements, and the light detector includes one or more light detecting elements. A first opaque light barrier portion, between the light source and the light detector, is configured to block light from being transmitted directly from the light source to the light detector. A second opaque light barrier portion, extending from the first opaque light barrier portion in a direction towards the light source, is configured to reduce an amount of specular reflections that would occur if a light transmissive cover plate were placed over the optical sensor device.Type: ApplicationFiled: December 21, 2009Publication date: October 14, 2010Applicant: INTERSIL AMERICAS INC.Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
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Publication number: 20100261344Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.Type: ApplicationFiled: June 28, 2010Publication date: October 14, 2010Applicant: INTERSIL AMERICAS INC.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, JR., David A. Decrosta, Robert L. Lomenick, Chris A. McCarty
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Publication number: 20100258712Abstract: An optical sensor device comprises a light source, a light detector, and an opaque light barrier including a first portion to block light from being transmitted directly from the source to the detector. A second portion of the light barrier extends from the first portion in a direction towards the light source, such that a portion of the second portion covers at least a portion of light emitting element(s) of the source, to reduce an amount of specular reflections, if a light transmissive cover plate were placed over the sensor. Additionally, a third portion of the barrier can extend from the first portion, in a direction towards to the detector, such that a portion of the third portion covers at least a portion of light detecting element(s) of the detector, to reduce an amount of specular reflections that would be detected by the detecting element(s) of the detector, if a light transmissive cover plate were placed over the sensor. Additionally, an off-centered lens can cover a portion of the light source.Type: ApplicationFiled: July 8, 2009Publication date: October 14, 2010Applicant: INTERSIL AMERICAS INC.Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
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Publication number: 20100259279Abstract: An integrated circuit comprises at least one pin and has at least one resistor connected between a reference voltage and the at least one pin. Current measurement circuitry applies a voltage across the at least one resistor and measures a current at the at least one pin responsive to the applied voltage in a first mode of operation. The measured current enables determination of a current limit set point for the integrated circuit. In a second mode of operation, the at least one resistor comprises a pull up resistor and the at least one pin that is connected to the at least one resistor comprises an open-drain output.Type: ApplicationFiled: June 11, 2009Publication date: October 14, 2010Applicant: INTERSIL AMERICAS INC.Inventors: WILLIAM BRANDES SHEARON, LAWRENCE GILBERT GOUGH
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Publication number: 20100259766Abstract: Provided herein are optical sensor devices, methods for making the same, and systems including the same. An optical sensor device, according to an embodiment, includes a light detector die and a light source die attached to the same or different die attachment substrates so that there is a space between the light source die and the light detector die. A light transmissive material covers the light detector die, the light source die and at least a portion of the space between the light detector die and the light source die. A groove is formed (e.g., saw, blade or laser cut, or cast) in the light transmissive material between the light detector die and the light source die, and an opaque material is put within the groove to provide a light barrier between the light detector die and the light source die.Type: ApplicationFiled: July 8, 2009Publication date: October 14, 2010Applicant: INTERSIL AMERICAS INC.Inventors: Lynn K. Wiese, Nikhil Kelkar, Viraj Patwardhan
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Patent number: 7813247Abstract: Provided herein are hybrid laser diode drivers (LDDs) that drive a laser diode in response to receiving enable signals from a controller. In accordance with specific embodiments, a hybrid LDD includes a read channel to selectively output a read current, one or more write channel each to selectively output a write current, and an oscillator channel to selectively output an oscillator current. Additionally, in specific embodiments the hybrid LDD includes a decoder that receives the enable signals from the controller, and based on the enable signals, controls timing of the currents output by the read, write and oscillator channels.Type: GrantFiled: May 16, 2007Date of Patent: October 12, 2010Assignee: Intersil Americas Inc.Inventors: Theodore D. Rees, Akihiro Asada
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Patent number: 7812581Abstract: A multiphase regulator which includes an output node developing an output voltage, a feedback circuit determining error of the output voltage and providing a compensation signal indicative thereof, at least three phase circuits coupled in parallel to the output node, and an adaptive controller. Each phase circuit includes a modulation circuit and a switch circuit. Each modulation circuit receives the compensation signal and generates pulses on a corresponding one of the pulse modulation signals. Each switch circuit is coupled to the output node and is controlled by a corresponding pulse modulation signal. The adaptive controller is responsive to a load indication signal, such as indicating a low load condition, and drops operation of at least one of the phase circuits and adds at least one pulse to a pulse modulation signal of each remaining phase circuit.Type: GrantFiled: December 12, 2007Date of Patent: October 12, 2010Assignee: Intersil Americas Inc.Inventors: Weihong Qiu, Robert H. Isham, Chun Cheung
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Publication number: 20100252871Abstract: Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the present invention are also directed to methods of providing such light sensors, and methods for using such light sensors.Type: ApplicationFiled: June 16, 2010Publication date: October 7, 2010Applicant: INTERSIL AMERICAS INC.Inventors: Alexander Kalnitsky, Dong Zheng, Joy Jones, Xijian Lin, Gregory Cestra
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Patent number: 7808872Abstract: Provided herein are hybrid laser diode drivers (LDDs) that drive a laser diode in response to receiving enable signals from a controller. In accordance with specific embodiments, a hybrid LDD includes a read channel to selectively output a read current, one or more write channel each to selectively output a write current, and an oscillator channel to selectively output an oscillator current. Additionally, in specific embodiments the hybrid LDD includes a state machine that receives the enable signals from the controller, and based on the enable signals, controls timing of the currents output by the read, write and oscillator channels.Type: GrantFiled: May 16, 2007Date of Patent: October 5, 2010Assignee: Intersil Americas Inc.Inventors: Theodore D. Rees, Akihiro Asada
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Patent number: 7807555Abstract: This disclosure describes an improved process and resulting structure that allows a single masking step to be used to define both the body and the threshold adjustment layer of the body. The method consists of forming a first mask on a surface of a substrate with an opening exposing a first region of the substrate; implanting through the opening a first impurity of a first conductivity type and having a first diffusion coefficient; and implanting through the opening a second impurity of the first conductivity type and having a second diffusion coefficient lower than the first diffusion coefficient. The first and second impurities are then co-diffused to form a body region of a field effect transistor. The remainder of the device is formed.Type: GrantFiled: October 11, 2007Date of Patent: October 5, 2010Assignee: Intersil Americas, Inc.Inventor: Michael Curch
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Publication number: 20100245145Abstract: An resistor string digital-to-analog converter (DAC) that includes elements to compensate for resistor ladder loading, and/or to provide compensation for loading such as via switch current cancellation. The approach reduces output voltage sensitivity to switch resistances while also reducing INL and DNL errors. Additional resistor loops are optionally disposed at the top and bottom of one or more further segments to provide Nth order resistive current cancellation.Type: ApplicationFiled: February 26, 2010Publication date: September 30, 2010Applicant: Intersil Americas, Inc.Inventor: Ali Motamed
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Publication number: 20100244799Abstract: A multi-phase voltage regulator comprisies a plurality of current supplying stages, each current supplying stage configured to supply a local output current equaling at least a portion of a load current output from the multi-phase voltage regulator; and a plurality of control circuits, each control circuit coupled to a respective one of the plurality of current supplying stages, wherein each control circuit calculates a control signal based, at least in part, on a sampled current representative of the respective local output current and a sampled current representative of a master output current. The control signal from each control circuit causes the respective current supplying stage to be disabled gradually over a first time interval if the sum of the local output current and the master output current is detected as being below a respective first predetermined level.Type: ApplicationFiled: March 24, 2010Publication date: September 30, 2010Applicant: INTERSIL AMERICAS INC.Inventor: Zaki Moussaoui
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Patent number: 7804143Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.Type: GrantFiled: February 18, 2009Date of Patent: September 28, 2010Assignee: Intersil Americas, Inc.Inventors: Stephen Joseph Gaul, Michael D. Church, Brent R. Doyle
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Patent number: 7800352Abstract: A modulation controller includes an error amplifier which receives a reference voltage and an output voltage (VOUT) from a switching regulator being controlled by the controller at its inputs and provides a VCOMP signal at its output, and at least one comparator, wherein a first input of the comparator is coupled to an output of the error amplifier and a second input coupled to receive a ramp signal. A VCOMP shift cancellation circuit is interposed between the first or second input of the comparator, wherein the VCOMP shift cancellation circuit improves diode conduction mode performance (DCM) of the regulator by reducing a variation in average VCOMP.Type: GrantFiled: July 16, 2007Date of Patent: September 21, 2010Assignee: Intersil Americas Inc.Inventors: Weihong Qiu, Robert Isham
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Patent number: 7796365Abstract: A DC-DC converter includes a chip including an error amplifier and a pulse width modulator (PWM) having an input connected to an output of the error amplifier, and an inductor driven by said PWM in series with an output node (VOUT) of the converter, wherein a load current flows through the inductor. VOUT is fed back through a network including a feedback resistor (RFB) to an inverting input of the error amplifier. A circuit for sensing the load current includes a first operational amplifier, a sense resistor on the chip having resistance RSENSE coupled to an inverting input of the first amplifier; wherein a sense current related to the load current flows through the sense resistor, a dependent current source provides an output current to supply the sense current. A reference resistor is disposed on the chip having a resistance RREFERENCE which is a fixed multiple of RSENSE. A set resistor is provided having a resistance RSET.Type: GrantFiled: March 23, 2009Date of Patent: September 14, 2010Assignee: Intersil Americas Inc.Inventor: Robert H. Isham
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Patent number: 7795130Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.Type: GrantFiled: April 19, 2007Date of Patent: September 14, 2010Assignee: Intersil Americas Inc.Inventors: John T. Gasner, Michael D. Church, Sameer D. Parab, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick, Chris A. McCarty