Abstract: Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When in the first configuration, the second input/output node follows the first input/output node. When in the second configuration, the first input/output node follows the second input/output node.

Abstract: A circuit comprises a first input for receiving a supply voltage and a second input for receiving a sensed current signal from an output of a DC to DC converter. The circuit also includes an output voltage for providing an adjustable drive voltage to a drive circuit. The circuit additionally includes circuitry for adjusting the drive voltage responsive to supply voltage and the sensed current signal.

Abstract: A multiphase boost converter includes a multiphase PWM controller for generating a plurality of PWM signals. A plurality of boost converters are each associated with a separate phase connected between an input voltage node and an output voltage node and generating an output voltage responsive to an input voltage and the plurality of PWM signals. Phase nodes of each of the plurality of boost converters are ORed to each other.

Abstract: Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.

Abstract: A silicon-controlled rectifier (SCR) device having a high holding voltage includes a PNP transistor and an NPN transistor, each transistor having both p-type and n-type dopant regions in their respective emitter areas. The device is particularly suited to high voltage applications, as the high holding voltage provides a device which is more resistant to latchup subsequent to an electrostatic discharge event compared to devices having a low holding voltage.

Abstract: A switch circuit including a first switch, a reference device, a current generating device and a comparator. The first switch has a first resistance and develops a first voltage when a first current is provided through it. The reference device has a second resistance which is a known multiple of the first resistance. The current generating device provides a reference current through the reference device which develops a second voltage having a level indicative of a maximum current level of the first current. The comparator compares the first and second voltages and provides a maximum current indication. An amplifier may be used to force one side of the first switch and the reference device to the same voltage, where the reference device is coupled between an input and an output of the amplifier. The switch circuit may include a calibration mode.

Abstract: Circuits and methods for damping out parasitic resonance within a packaged integrated circuit (IC) are provided. A conductive path including a resistor and a conductor is added in parallel with a conductive path that provides power to components within a die of the packaged IC. When implemented in a packaged laser driver integrated circuit (IC), a conductive path including a resistor and a conductor in placed in parallel with a conductive path that provides a laser driver output, of the packaged laser driver IC, to a laser diode. This abstract is not intended to be a complete description of the various embodiments of the present invention.

Abstract: An apparatus for charging a plurality of series connected battery cells includes first and second input terminals for providing a charging voltage to the plurality of series connected battery cells. A transformer includes a primary side associated with the charging voltage and a secondary side including a plurality of portions. Each of the plurality of portions connected across at least two of the plurality of series connected battery cells. A first switch in series between each of the plurality of portions of the secondary side and a first battery cell of the at least two of the plurality of series connected battery cells provides a charging current to the first battery cell during a first portion of a cycle of a current in the primary side of the transformer.

Abstract: An apparatus for charging a plurality of series connected battery cells, includes a first and second input terminals for providing a charging voltage to the plurality of series connected battery cell. A transformer includes a primary side associated with the charging voltage and a secondary side includes a plurality of portions. Each of the plurality of portions is connected across at least one of the plurality of series connected battery cell. A switch in series between each of the plurality of portions of the secondary side and the at least one of the plurality of series connected battery cells increases an impedance between the portion of the secondary side and the associated one of the plurality of series connected battery cells in a first state and decreases the impedance between the portion of the secondary side and the associated one of the plurality of series connected battery cells in a second state.

Abstract: A two-channel time-interleaved analog-to-digital converter (TIADC) system that provides for estimation and correction of offset, gain, and sample-time errors. Error in the offsets of the two ADCs that form the TIADC produces a spurious signal at the Nyquist frequency that can be used to minimize the difference of offsets of the ADCs. The difference in gain between the two ADCs produces spurious signals reflected around the Nyquist frequency whose magnitudes can be reduced by minimizing the difference in signal power between the two ADCs. An Automatic Gain Control loop corrects the scaling of the input signal due to the average of the gains of the ADCs. Phase error produces spurious signals reflected around the Nyquist frequency that are ?/2 out of phase with those due to the gain error. Minimizing the difference between the correlation of consecutive signals from the ADCs reduces the magnitude of these image tones.

Abstract: Techniques for correcting component mismatches in an M-channel time-interleaved Analog to Digital Converter (ADC). In order to obtain an error measure for offset, gain or phase, errors, outputs from each ADC are either summed or averaged over No samples. Calling each of the sums or averages as Xk where k=1, 2, . . . , M, there are M such values as a result. A single value representing the mean of these M values, Xmean, is chosen as a reference value. The offset, gain and phase errors for the M different ADCs are then obtained from Xk?Xmean. The sign of each offset error, i.e., sign (Xk?Xmean), is then used to drive an adaptive algorithm whose output represents an offset correction value for the corresponding ADC. The offset, gain, and phase correction outputs from the adaptive algorithm is fed to an array of Digital-to-Analog converters (DACs) whose outputs are voltages or currents that directly or indirectly controls the offset, gain or phase setting of each individual ADC.

Abstract: An AC power supply system modulates a high frequency switching signal with a pulse width modulation (PWM) signal to produce a composite signal. The duty cycle of the PWM component of the composite signal is used to control the brightness of a cold cathode fluorescent lamp for backlighting a liquid crystal display.

Abstract: A zero volt switching voltage converter comprises a switching network including a plurality of switches for generating control signals responsive to an input voltage source and switching control signals. Circuitry generates a regulated output voltage responsive to the control current. Control circuitry generates the switching control signals wherein the switching control signals operate the plurality of switches at a resonant frequency of the zero volt switching voltage converter.

Abstract: Pulse width modulation (PWM) controllers and output stage driver circuits and related methods of communicating switching regulator mode information. The controller includes circuitry that recognizes intervals when the load driven by the regulator is in a low power mode. Responsive to recognizing the low power mode, the controller generates a PWM mode signal having at least three (3) different levels including at least one intermediate level that is coupled to at least one driver. Based on the PWM mode signal, the regulator is switched into a power saving low power operational mode.

Abstract: A communication system comprising a first and second transceiver is provided. The first transceiver has a first and second port coupled to a communication medium, wherein a first differential capacitor couples the first and second ports together. The second transceiver has a third and fourth port each AC coupled to the communication medium, wherein a second differential capacitor couples the third and fourth ports together.

Abstract: In accordance with an embodiment of the invention, there is an integrated circuit device having a complementary integrated circuit structure comprising a first MOS device. The first MOS device comprises a source doped to a first conductivity type, a drain extension doped to the first conductivity type separated from the source by a gate, and an extension region doped to a second conductivity type underlying at least a portion of the drain extension adjacent to the gate. The integrated circuit structure also comprises a second complementary MOS device comprising a dual drain extension structure.

Abstract: A junction barrier Schottky diode has an N-type well having surface and a first impurity concentration; a p-type anode region in the surface of the well, and having a second impurity concentration; and an N-type cathode region in the surface of the well and horizontally abutting the anode region, and having a third impurity concentration. A first N-type region vertically abuts the anode and cathode regions, and has a fourth impurity concentration. An ohmic contact is made to the anode and a Schottky contact is made to the cathode. The fourth impurity concentration is less than the first, second and third impurity concentrations.

Abstract: A cradle charging system comprises a charging cradle defining a space for a battery of an electronic device. Transformer charging circuitry for charging the battery in the electronic device includes a primary side circuitry for receiving a charging voltage. Secondary side circuitry inductively couples the charging voltage to the battery. The secondary side circuitry provides a controlled output signal based on either constant voltage control or constant current control responsive to a charge level of the battery.

Abstract: Provided herein are optical sensor systems that can be used for ambient light detection, proximity detection and motion detection, as well as to larger systems that include such an optical sensor system, and to related methods. In an embodiment, the optical sensor system includes a front end, an ambient light channel, a proximity channel and a motion channel. In an embodiment, offset and gain of the proximity channel is adjusted based on motion detected by the motion channel.

Abstract: A method for allowing measurement corrections on a chip-by-chip basis. Error correction values are generated responsive to the input value to a circuit of the calibrated integrated circuit chip and to a measured value from the circuit of the calibrated integrated circuit chip. The error correction values are stored within an error correction table within a nonvolatile memory of the integrated circuit chip.