Abstract: A method for calibrating read data strobe gating including the steps of: (A) performing a coarse timing adjustment configured to determine a coarse delay setting that produces invalid data, (B) performing a medium timing adjustment configured to adjust a medium delay setting and the coarse delay setting until valid data is detected, (C) performing a fine timing adjustment configured to adjust the medium delay setting and a fine delay setting until valid data is detected and (D) adding one-half cycle to a gating delay determined by the coarse, the medium and the fine delay settings.

Abstract: A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STE) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.

Abstract: An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.

Abstract: A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.

Abstract: An apparatus comprising a first processing circuit and a second processing circuit. The first processing circuit may be configured to generate (i) one or more prediction samples and (ii) a plurality of macroblocks, in response to each frame of an input video signal. The second processing circuit may be configured to (i) select one or more reference indices for each of the macroblocks from one or more sets of reference indices and (ii) generate said one or more prediction samples in response to said selected reference indices. Each of the selected reference indices is generally determined based upon minimum and maximum values for each of the one or more sets of reference indices.

Abstract: A method and computer readable storage medium for estimating total path delay in an integrated circuit design include of receiving as input a number of stage delays and stage delay variations constituting a path in an integrated circuit design. A sum of the stage delays, a worst case sum of the stage delay variations, and a root-sum-square of the stage delay variations are calculated. A a value of a weighting function is calculated as a function of the number of stage delays. A a weighted sum of the worst case sum of the stage delay variations and the root-sum-square of the stage delay variations is calculated from the weighting function. The weighted sum is generated as output to estimate total path delay.

Abstract: A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at least one daughter card is connected to the motherboard so that the daughter card is communicatively connected to common memory provided on the motherboard. The motherboard is connected to an information handling system utilizing a prototyping interface device, the information handling system providing a virtual software modeling environment for an integrated circuit. The at least one daughter card, information handling system, prototyping interface device and motherboard emulate an integrated circuit design. At least one of software and system integration of the integrated circuit emulated by the motherboard, information handling system, prototyping interface device and the at least one daughter card is tested.

Abstract: The present invention is directed to a customizable development and demonstration platform for structured ASICs. In an exemplary aspect of the present invention, the present platform may include a structured ASIC which is built on a slice and which may be flexible enough for a number of possible application developments. This flexibility may be achieved by incorporating a programmable processor in the structured ASIC and by defining interfaces and the use of an external FPGA in the present platform. The structured ASIC may include a complete ARM processor subsystem and a plurality of high speed SERDES ports. The processor subsystem may include a bus interface to the external FPGA, allowing custom gate development and test in the FPGA, prior to incorporating it into the customer product. Through the SERDES ports, the test block may be used to show the electrical characteristics of the SERDES IP. In addition, some SERDES ports may be driven from a link layer realized in the FPGA.

Abstract: The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in machine-readable memory and are updated in response to wire changes within the design field.

Abstract: Cells are placed into an integrated circuit floorplan by creating clusters of cells in modules, each cluster being composed of cells in a path connected to at least one flip-flop in the module, or of cells that are not in a path connected to any flip-flop. Regions are defined in the floorplan for placement of modules, and the clusters are placed into optimal locations in modules and placing the modules into optimal locations in the regions. The coordinates for the wires, modules and clusters are selectively recalculated. The clusters are moved in the floorplan for more uniform density, and the modules are assigned to regions based on module coordinates.

Abstract: The invention may relate to a method of programming a programmable non-volatile device. The programmable non-volatile device may be programmed while coupled to a circuit in which the programmable non-volatile device is to be used. The method may include establishing a connection and communicating information. The connection may be established from an external device to a test interface of the circuit. The information may be communicated from the external device through the test interface, for programming the programmable non-volatile device.

Abstract: The present invention provides a system and method for implementing postponed quasi-masking test output compression in an integrated circuit. The system includes a compressor for compressing a test response from N scan chains of an integrated circuit into M outputs. The test response may indicate faults in the integrated circuit. M and N are positive integers. The system further includes a correctable multiple input signature register with a size of M, which is communicatively coupled to the compressor. The correctable multiple input signature register is suitable for receiving the M outputs from the compressor as data inputs (s[0], . . . , s[M?1]) and receiving M correction bits (c[0], . . . , c[M?1]) and L address bits (a[0], . . . , a[L?1]) as correction inputs, L being a positive integer, 2L>=M. The correctable multiple input signature register is suitable for detecting faults when there is no or at least one unknown value (i.e., X-value) in the test response.

Abstract: Improved methods and structures for testing of SAS components, in situ, in a SAS domain. A first SAS component is adapted to generate stimuli such as error conditions to elicit a response to the error condition from a second SAS component coupled to the first in the intended SAS domain configuration. In one aspect, a SAS device controller generates stimuli applied to a SAS expander coupled thereto and verifies proper response from the SAS expander. In another aspect, a SAS expander generates stimuli applied to a SAS device controller coupled thereto and verifies proper response from the SAS device controller. Stimuli may be generated by custom circuits or firmware/software within the first component. Vendor specific SAS SMP transactions may be used to cause the first component to enter the special verification mode.

Abstract: A method is provided for selecting a frequency-based ramptime limit for a technology. The method includes creating a logic chain with cells from the technology and applying a sequence of signals to the logic chain. Each signal has a different ramptime relative to a clock period. At least one signal quality characteristic is measured along the logic chain for each of the signals. The frequency-based ramptime limit is selected based on a comparison of the measured signal quality characteristics measured to at least one predefined signal quality value.

Abstract: A contact ring for use in electroplating of a substrate material is constructed such that fluid (e.g., electrolyte) is allowed to flow radially away from the axis of a toroidal support ring, thus preventing the trapping of fluids between the substrate and the toroidal support ring. The contact ring is constructed with a series of openings arranged about the circumference of the ring and wherein an electrical contact is placed in the path of each opening so any fluid passing through the opening also passes around the associated electrical contact. Further, the electrical contacts are also placed such that a substrate (e.g., a semiconductor wafer) can be placed inside the support ring so as to electrically contact the electrical contacts. The toroidal support ring has an aerodynamically streamlined cross-section at the openings, such that fluid flows through the openings with reduced aerodynamic drag.

Abstract: A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation. A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.

Abstract: The digitally programmable delay circuit to correct timing skew between data and clock is developed. The digitally programmable delay circuit may be built by cascading delay cells. The delay circuit uses delay cells comprising simple digital elements such as inverters and tri-state inverters to eliminate the intrinsic delay and achieves linearity and monotinicity. The delay cell may be used as a building module which is repeatedly used in a serial fashion. The delay range is fully programmable from the delay of one delay cell to infinity if the chip area is available. The delay range can be scaled by adding more delay cells.

Abstract: A memory controller system is provided, which includes a plurality of system buses, a multi-port memory controller and a plurality of error correcting code (ECC) encoders. The memory controller has a plurality of system bus ports and a memory port. Each ECC encoder is coupled between a respective system bus and a respective system bus port of the memory controller.

Abstract: A method and system for controlling electronic component configuration. The system includes a guard including an aperture and a plate including an aperture are adjustably connected. The guard and the plate each include a pin connected thereto. The system is capable of adjusting configurations to obtain an open configuration where at least a portion of the guard and plate apertures align and a blocked configuration where the plate and the guard apertures fail to permit access. Depending on an introduced component characteristic the component's physical keying structure may be received or prevented depending on the implementation. Additionally the present invention permits retrofitting a component with a correct characteristic but lacking a keying structure by disposing plate/guard pins outside the footprint of an introduced electronic component.

Abstract: A method of tiling a customer memory design to configurable memory blocks within a standardized memory matrix. A customer memory capacity and a customer memory width is determined for the customer memory design, and a standardized memory capacity and a standardized memory width is determined for the configurable memory blocks. The customer memory capacity and the customer memory width are selectively transformed by inverse factors based at least in part on a comparison of the customer memory capacity and the standardized memory capacity. Case independent blocks are formed within the configurable memory blocks, where the case independent blocks include gate structures formed in a standardized array in a substrate in which the customer memory design is to be implemented.