Abstract: A method of tiling a customer memory design to configurable memory blocks within a standardized memory matrix. A customer memory capacity and a customer memory width is determined for the customer memory design, and a standardized memory capacity and a standardized memory width is determined for the configurable memory blocks. The customer memory capacity and the customer memory width are selectively transformed by inverse factors based at least in part on a comparison of the customer memory capacity and the standardized memory capacity. Case independent blocks are formed within the configurable memory blocks, where the case independent blocks include gate structures formed in a standardized array in a substrate in which the customer memory design is to be implemented.

Abstract: The present invention provides a segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits. A scan chain is divided into a plurality of segments. For a test pattern, compatible segments of the plurality of segments are grouped into compatibility classes. All compatible segments or a subset of them within one of the compatibility classes are simultaneously loaded through selective activation.

Abstract: A method is provided for selecting a frequency-based ramptime limit for a technology. The method includes creating a logic chain with cells from the technology and applying a sequence of signals to the logic chain. Each signal has a different ramptime relative to a clock period. At least one signal quality characteristic is measured along the logic chain for each of the signals. The frequency-based ramptime limit is selected based on a comparison of the measured signal quality characteristics measured to at least one predefined signal quality value.

Abstract: A plurality of selectable memory devices is available for booting a computer processor. The devices may be selected prior to booting, or may be changed upon recognition that the booting process is not proceeding properly. In another use, one device may be reprogrammed with an updated version while keeping the older version present. Once the updated version is functioning properly, the older version may be overwritten so that two known working copies are available.

Abstract: An electromagnetic polish head (100) comprises at least one electromagnet. An embodiment may also include the addition of a slurry component or components that can be affected by an electromagnetic field. During polishing or planarization, a field or fields may be generated by the polish head (100) to affect the polishing of a wafer by attracting or repelling the slurry to a portion or portions of the substrate.

Abstract: An apparatus comprising a de-interlacer circuit, a rate converter circuit and a zoom circuit. The de-interlacer circuit may be configured to generate a first progressive signal having a first rate in response to an interlaced signal. The rate converter circuit may be configured to generate a second progressive signal having a second rate in response to the first progressive signal. The zoom circuit may be configured to generate an output video signal in response to the second progressive signal. The output video signal may represent a portion of the second progressive signal having a frame size equal to a frame size of the interlaced signal.

Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.

Abstract: Methods and structure for improved high-speed TDF testing using an on-chip PLL and associated logic to generate high speed launch and capture pulses. A reference clock may be applied to a PLL circuit within the integrated circuit under test to generate a higher frequency PLL Clock. Gating Logic features and aspects within the integrated circuit may apply the PLL Clock signal to a TDF Clock signal when so directed by a TDF Enable signal from an external test system. The PLL Clock is applied to the TDF Clock signal path for precisely two clock pulses for use as a launch and capture pulse sequence for TDF testing at higher speeds than the external automated test system may achieve.

Abstract: A wafer chuck is configured to hold a wafer efficiently for spin process cleaning of wafer edges and back sides. A first group of retractable tips extend to hold the wafer during a first portion of the cleaning period. A second group of retractable tips extend to hold the wafer during a second portion of the cleaning period. Residues left between the tips and the wafer edge areas during the first portion of the cleaning period are removed during the second portion. The change from the first group of tips to the second group of tips occurs while the wafer is rotating.

Abstract: The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floating rectangle which may represent a search table of the longest prefix search engine, a coding module for providing address and prefix information to the longest prefix search engine, a mapping module for providing data information to the longest prefix search engine, a super search engine for performing super search operations, and an analyzer for computing predicted outputs of the longest prefix search engine and for comparing the predicted outputs with actual outputs computed by the longest prefix search engine.

Abstract: A method of generating a timing model for a customer memory configuration, by generating a plurality of template memory netlists for a given RRAM design. Timing models for the template memory netlists are produced and stored in a first database. The template memory netlists are stored in a second database. A netlist for the customer memory configuration is generated and compared to the template memory netlists to find a match. When a match is found, one of the timing models that is associated with the matching template memory netlist is used as the timing model for the customer memory configuration. When a match is not found, two of the template memory netlists that bound the customer netlist are found, according to at least one parameter, and the timing model for the customer memory configuration is interpolated based on the two bounding template memory netlists.

Abstract: A pad groove analyzer and associated method configured to assess the grooves on the pad and determine how worn the pad is. The pad groove analyzer may be configured to monitor the grooves via a contact or no-contact process. In a contact process, the pad groove analyzer may include a stylus which physically contacts and moves along the pad. As the stylus falls into the grooves in the pad as the stylus moves along the pad, signals are created, and a stylus monitor uses the signals to determine to what extent the pad is worn. The stylus monitor can be configured to communicate with the general tool controller. In a no-contact process, the pad groove analyzer may take several different forms.

Abstract: A system for providing spectral compensation for vestigial sideband, VSB, signals with carrier frequency error. The VSB signal is sampled and digitized. The carrier frequency of the digitized signal is translated to a selected IF frequency. A fixed frequency VSB filter is then used to provide spectral compensation for the signal.

Abstract: An apparatus for variably scaling video picture signals comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more data signals vertically scaled to a first value in response to (i) the video picture signals and (ii) one or more control signals. The second circuit may be configured to generate one or more output signals horizontally scaled to a second value in response to (i) the one or more data signals and (ii) the one or more control signals. The first value and the second value are independently selectable.

Abstract: A method for floorplan visualization comprising the steps of (A) receiving design information for an integrated circuit design comprising one or more subsystems, (B) generating one or more gate count estimates for the one or more subsystems of the integrated circuit design, (C) generating one or more gate density estimates for gates of the one or more subsystems mapped to one or more programmable areas of a programmable platform device and (D) generating a visual representation of one or more area estimations for each of the one or more subsystems based on the one or more gate count estimates and the one or more gate density estimates.

Abstract: A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

Abstract: The present invention is directed to a removable cage for a computer chassis assembly. Such cage is comprised of a frame. The frame includes a top, a bottom and two sides. In an exemplary embodiment, a midplane is coupled to the frame for providing a place to mount at least one disk drive. The midplane may include a midplane cover plate. Such plate provides protection to the midplane upon removal and insertion of the midplane. In an exemplary embodiment, the midplane cover plate is operationally coupled to the midplane which is in turn coupled to the frame via tooling pins. Finally, a plurality of fasteners are coupled to the frame for attaching the frame to the midplane and computer chassis assembly. The fasteners align and mount the frame including the midplane to the computer chassis assembly allowing for removal of the midplane without affecting the computer chassis configuration.

Abstract: An RRAM flip-flop rcell memory of the type having a write address decoder, a read address decoder, a set of n flip flops, one AND gate associated with each flip flop in the set, a set of w OR gates where each of the w OR gates in the set has n inputs, the improvement comprising only one write address decoder, and replacing the read address decoder and the set of AND gates and the set of OR gates with no more than one multiplexor, thereby providing a reduction in a path length from an rcell memory input to an rcell memory output and thereby improving timing of the rcell memory, while reducing fanout size of the rcell. In a preferred embodiment, the multiplexor includes fewer than w OR gates, and fewer than n AND gates, and two decoders, which are commonly connected to outputs of the n flip flops.

Abstract: A system and method for indicating the service status of serviceable elements of a subassembly stores the service status in a memory using a host controller. When the subassembly is removed from the host controller, the memory may be accessed using a second circuit and separate power supply, and indicators may be illuminated to indicate the service status of the elements.

Abstract: The present invention provides a layout method for a top module including instances of a base module in a memory matrix such as a RRAM memory matrix, and the like. The top module and the base module may each include data pins and at least one control pin, or the top module and the base module may each include data pins only and may not include any control pins. The data pins of the instances of the base module are replicated in the top module. When at least one control pin is included in the top module and the base module, a control signal may be shared among the instances of the base module and the top module by tying together corresponding control pins of the instances and a corresponding control pin of the top module. The present method may include steps as follows. At a library preparation stage, data pins (and control pins, if applicable) of standard cells in the top module are extended vertically for easy access.