Abstract: The present invention relates to a method, circuit, and system for performing write journal operations on a bus interface controller board or bus interface controller integrated circuit chip. This is achieved by placed a write journal memory on the board or chip and supplying power to it from an external power source. Preferably, the external power source is a battery. The internal memory may use bus interface controller power when available to prolong battery life.

Abstract: A branch predictor, a method of predicting a conditional branch and a digital signal processor incorporating the conditional branch predictor or the method. In one embodiment, the branch predictor includes: (1) static branch correction logic configured to employ a static branch prediction and a correction indicator associated with a particular conditional branch in a computer program to generate a corrected branch prediction pertaining to the particular conditional branch and (2) confidence state updating logic associated with the static branch correction logic and configured to employ the static branch prediction and a branch taken indicator associated with the particular conditional branch to update a confidence state associated with the particular conditional branch, the correction indicator based on the confidence state.

Abstract: A method for implementing a circuit design is disclosed. The method generally includes the steps of identifying, replacing and routing. The first step may identify a first cell of the circuit design having (i) a function and (ii) an input pin connectable to one of a first power rail and a second power rail having a different voltage than the first power rail. The second step may replace the first cell with a second cell having (i) the function, (ii) the input pin and (iii) at least one blocking characteristic that reserves (a) a first route completely within a particular conductive layer of the cell between the input pin and the first power rail and (b) a second route completely within the particular conductive layer between the input pin and the second power rail. The third step may route the circuit design incorporating the second cell such that the input pin is connected to one of (i) the first power rail using the first route and (ii) the second power rail using the second route.

Abstract: The present invention provides a filter circuit, related method of operating the filter circuit and a digital signal processing circuit incorporating the same. In one embodiment, the filter circuit includes a conditioning stage, operable at a rate corresponding to an input signal to be sampled, configured to derive an intermediate signal from the input signal as a function of a parameter. The filter circuit further includes an output stage, operable at a sampling rate, configured to derive a sampled signal as a function of the intermediate signal where the parameter is adapted to govern characteristics of a frequency response associated with the sampled signal.

Abstract: An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Abstract: A receiver detector of a peripheral device for use in a computer system to detect whether a receiver is electrically coupled to a data port of the peripheral device includes a modulator, a high pass filter, and a demodulator. The modulator is configured to modulate a receiver detect signal at a frequency that is higher than a noise frequency, below which high amplitude noise can develop. The high pass filter is electrically coupled to the receiver detect signal and is configured to block frequencies of the receiver detect signal that are below the noise frequency and pass a filtered receiver detect signal. The demodulator is configured to demodulate the filtered receiver detect signal and produce a recovered receiver detect signal that is indicative of whether a receiver is electrically coupled to the data port.

Abstract: A test methodology which provides that test structures, such as transistors, are arranged in a plurality of rows. A logic circuit controls which row is to be measured. An incrementer receives a triggering signal and functions as an address adder. Each time the triggering signal rises from 0 to 1, the output of the incrementer increases by 1. The output of the incrementer serves as the address input into a decoder. The decoder is connected to the rows of test structures. Preferably, each test structure contains a control circuit which is controlled by this signal (i.e., the output of the decoder). If the test structures are transistors, bias to each of the transistors can be applied separately with a common gate, source and well, and measurement can be done with a separate drain node.

Abstract: An underfill includes a base material and a filler material added to the base material wherein the filler material constitutes a selected percentage by weight of the underfill to provide an optimum balance between interfacial die stress and solder bump strain for next generation, Cu, low-K silicon technology.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: The present invention provides methods and apparatus for accomplishing a strong phase shift direct write lithography process using reconfigurable optical mirrors. A maskless lithography system is provided. The maskless direct-write lithography system provided uses an array of mirrors configured to operate in a tilting mode, a piston-displacement mode, or both in combination. The controlled mirror array is used to generate strong phase shift optical patterns which are directed onto a photoimageable layer of a substrate in order to facilitate pattern transfer. In order to avoid constraining the system to forming edges of patterns aligned with the array of mirrors, gray-scale techniques are used for subpixel feature placement.

Abstract: An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Abstract: A method and system is provided for handling unused structures in a slice during custom instance creation to avoid the need of a boundary scan synthesis tool, wherein the slice includes an embedded boundary scan chain having a particular length and order. Aspects of the present invention include using a software tool during slice creation to create at least one slice connectivity file. During instance creation, a customer designs a custom chip using the software tool by selecting which structures are to be use on the slice. The slice connectivity file is then reused for the instance by reading the connectivity file to determine which structures in the file are used and not used based on the customer's selections. Thereafter, the slice is reconfigured to include dummy logic in unused structures, such that the boundary scan chain retains the same length and order.

Abstract: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.

Abstract: A method of removing an edge bead of a coated material on a substrate. The substrate is rotated, and a fluid that solvates the coated material is delivered. The delivery of the fluid is directed radially inward on the substrate at a rate of between about three millimeters per second and about twenty millimeters per second until a desired innermost fluid delivery position on the substrate is attained. Immediately upon attaining the desired innermost fluid delivery position on the substrate, the delivery of the fluid is directed radially outward off the substrate at a rate of more than zero millimeters per second and less than about four millimeters per second. The rotation of the substrate is ceased.

Abstract: A device for measuring resistances associated with electrical contacts of a contact ring used in a semiconductor wafer electroplating process. The device includes a substrate and a conductive pattern on the substrate. The conductive pattern is electrically contactable with the electrical contacts of the contact ring. Resistance measurement circuitry is connected to the conductive pattern. The resistance measurement circuitry is configured to send test signals to the conductive pattern, receive signals from the conductive pattern, and measure the resistances associated with the electrical contacts of the contact ring. A method of using such a device to measure resistances associated with electrical contacts of a contact ring used in a semiconductor wafer electroplating process is also provided.

Abstract: The present invention is a method and apparatus for implementing a source synchronous interface in a platform using a Generic Source Synchronous Interface (GSSI) infrastructure. The GSSI infrastructure includes the GSSI bit slices and clock management system. The GSSI bit slice includes balanced cells and bit delay elements, and may be placed either within or close to IO buffers. The GSSI clock management system includes strategically placed frame delay elements with automatic on-chip calibration and control to satisfy various clock-data phase relationships. The GSSI methodology shows how different SSIs may be constructed by combining the common GSSI architecture with unique metal layer configurations. The GSSI architecture solves a critical challenge for platform-based design such as RapidChip™ and the like. The GSSI approach introduces a completely new way to implement various SSIs based on a common minimally diffused GSSI bit slice and clock management infrastructure.

Abstract: A method and computer program product for parasitic extraction from a previously calculated capacitance solution include steps of: (a) receiving as input a design database for an integrated circuit design; (b) receiving as input a first set of operating conditions and a second set of operating conditions for the integrated circuit design; (c) calculating a first resistance solution and a single capacitance solution from the design database and the first set of operating conditions; (d) performing a parasitic extraction of the first resistance solution and the single capacitance solution to generate a first set of parasitic values; (e) calculating a second resistance solution from the design database and the second set of operating conditions; (f) performing a parasitic extraction of the second resistance solution and the single capacitance solution to generate a second set of parasitic values; and (g) generating as output the first set of parasitic values and the second set of parasitic values.

Abstract: A semiconductor memory testing implementation suitable for build-in self repair (BISR) memories provides, in one embodiment, a memory testing circuit configuration including an output register for receiving digital data. A plurality of shift registers serially output the digital data to be received by the output register. Each one of the plurality of shift registers includes a feedback path for enabling the digital data output by a corresponding one of the plurality of shift registers to be input back into the corresponding shift register in a same sequence as the digital data is output from the corresponding shift register.

Abstract: An integrated circuit is provided, which includes a transistor device under test, an AC drive circuit, an AC bias circuit and a DC bias circuit. The AC drive circuit generates an AC drive signal. The AC bias circuit biases the transistor device under AC bias conditions in response to the AC drive signal. The DC bias circuit biases the transistor device under DC bias conditions. A switch circuit selectively couples the transistor device to the AC bias circuit in an AC stress mode and to the DC bias circuit in a DC measurement mode.

Abstract: A method of modular exponentiation includes receiving as input a first number, a second number, and a modulus for calculating a residue of a product of the first number times the second number modulo the modulus; partitioning the first number into a selected number of pieces; calculating a first product of one of the pieces times the second number; adding a previous intermediate result to the first product to generate a first sum; shifting the first sum by a selected number of bit positions to generate a second product; and reducing a bit width of the second product to generate an intermediate result wherein the intermediate result has a bit width that is less than a bit width of the second product and has a residue that is identical to a residue of the second product modulo the modulus.