Abstract: A unique memory access system and method to handle memory access requests to a memory shared by multiple independent data access devices (“IDADs”). More particularly, the present invention relates to a method and system that allows IDADs to efficiently execute memory access requests without having to wait for the shared memory to be available. In addition, the IDADs do not have to be designed to observe the specific memory protocol. The memory access requests from the IDADs are accepted by access request logic which then queues the requests. Memory access logic then executes the requests from the queue when the shared memory is available. The memory access logic places data obtained from read requests in a read buffer for the IDADs to access when convenient.

Abstract: A deposition ring which has a cut out on its interior circumferential edge. The deposition ring is configured to contact an edge of an electrostatic chuck and shield at least a portion of the electrostatic chuck during a deposition process wherein material is deposited onto an item, such as a semiconductor wafer, which is disposed on the electrostatic chuck. The interior circumferential edge of the deposition ring includes a surface portion which is configured to engage the edge of the electrostatic chuck, and includes the cut out portion which is configured to be spaced away and not contact the edge of the electrostatic chuck during the deposition process. As such, the deposition ring does not tend to bind with the electrostatic chuck during the deposition process.

Abstract: A process monitor circuit useful for integrated circuit designs to provide manufacturing process tests for SRAM circuit structures incorporated in an integrated circuit design. In one aspect of the invention, the process monitor cell includes a plurality of SRAM circuit cells chained together in a manner to permit testing of a desired range of SRAM transistor power and a desired range of associated propagation delays. The process monitor cell thereby provides an accurate estimate of the quality of the fabrication process used to generate other functional SRAM cells within the integrated circuit design.

Abstract: An asynchronous up-down counter includes a plurality of counter blocks. Each of the counter blocks has a counter output, an up-down control output, and an up-down control input. A counter signal output from each of the counter blocks has at least two bits. The asynchronous up-down counter also includes a signal bus coupling the up-down control output of a first counter block counting lesser significant bits to the up-down control input of a second counter block counting more significant bits. An up-down control signal output from each of the counter blocks has at least two bits. The up-down control signal may include a first control signal enabling counting operation of the second counter block and a second control signal indicating counting-up and counting-down.

Abstract: A method for verifying a path coverage of a circuit design. The method generally comprises the steps of implementing a hardware description language to include a plurality of monitors for a plurality of nodes of the circuit design, monitoring the nodes of a programmable circuit implementing the circuit design in real-time to capture node data, and assessing the node data to determine the path coverage.

Abstract: An apparatus for reducing residual oxygen content from a processing chamber of an atmospheric reactor after the processing chamber of the atmospheric reactor has been exposed to an oxygen environment. The processing chamber of the atmospheric reactor has an inert gas purge, including an inert gas source, for reducing a residual oxygen level within the processing chamber of the atmospheric reactor at a rate of reduction. A venturi vacuum system is enabled by the inert gas source. The venturi vacuum system draws a vacuum on the processing chamber of the atmospheric reactor and supplements the inert gas purge, thereby accelerating the rate at which the residual oxygen level is reduced within the processing chamber of the atmospheric reactor. In this manner, the vacuum created by the venturi vacuum system increases the efficiency of the inert gas purge by reducing by some moderate degree the pressure within the processing chamber of the atmospheric reactor.

Abstract: The present invention allows a user to draw a closed periphery around an amount of information on the display of a pen-based computer system. The periphery information is transmitted to the computer system by a digitizing tablet. When received by the computer system, the computer system divides the area enclosed by the periphery into a number of lines. The computer system then processes each of these lines and determines the information to erase on a given line.

Abstract: A serial data communication receiver includes a serial data input, first and second equalizers, first and second capture latch circuits, and an equalization control circuit. The first and second equalizers are coupled to the serial data input and have first and second equalized serial data outputs, respectively. Each equalizer has a frequency response that is variable over a range of frequency response settings. The first and second capture latch circuits are coupled to the first and second equalized serial data outputs, respectively, in a phase-locked loop and have first and second recovered data outputs, respectively. The equalization control circuit measures a data eye size of the second equalized serial data output over the range of frequency response settings of the second equalizer and sets the frequency response of the first equalizer to one of the frequency response settings based on the measured data eye sizes.

Abstract: A system has a plurality of enclosures. Each enclosure has two enclosure services modules. Each enclosure services module has an IN port and an EXPANSION port. Each enclosure services module is able to determine the data rate of incoming data and check the validity of this data. If the data rate is other than what the enclosure services module is set for, the data rate of the enclosure services module is changed to that of the incoming data. In the system, there are a disk array controller having a first channel and a second channel. The first channel is formed in sequence from a disk array controller to a first enclosure services module of a first enclosure and between first enclosure services modules of successive enclosures to a last enclosure. The second channel is formed in reverse sequence from the disk array controller to the second enclosure services module of the last enclosure and between second enclosure services modules of successive enclosures to the first enclosure.

Abstract: An apparatus comprising a transmit portion and a receive portion. The transmit portion may be configured to present (i) one or more data signals and (ii) a configuration signal, in response to one or more input signals. The receive portion may be configured to receive (i) all of the one or more data signals when operating in a first mode and (ii) less than all of the data signals when operating in a second mode. The first and second modes may be configured in response to the configuration signal.

Abstract: The present invention provides a method of forming SiGe gate electrodes using a thin nucleation layer. A dielectric layer is formed on a semiconductor wafer and a thin silicon nucleation layer deposited on top of the dielectric layer. A SiGe conducting film is deposited on the patterned silicon layer. The ratio of germanium to silicon in the gaseous source mixture for the silicon and germanium layer is selected so that the SiGe conducting film deposits on the nucleation layer but fails to deposit on the dielectric.

Abstract: A system for automatically migrating a portion of a collection of information located on source data carrier(s) into an assemblage of data carriers, having: a computer memory for pass-through of a first strip of the collection; the assemblage has at least a first storage medium to which at least a first sub-portion of the first strip is written from computer memory; and once the portion of the collection has been so migrated according to a predetermined structure, a remaining portion of the collection can be written to the source data carrier (to include the source data carrier in the assemblage), the remaining portion being ordered (crunched) in conformity with the predetermined structure.

Abstract: The present invention is directed to a system for providing a removable access panel for utilization with electronic devices. The panel of the present invention is connected to the frame of an electronic device through the use of a pocket hinge which allows a curved extension on the cover to engage a corresponding curved surface included in the pocket. Utilization of the present invention allows for the electronic device to maintain its overall provide while providing a hinge system allowing for ease of access and removable functionality.

Abstract: A circuit and associated methods of operation for a standardized scatter/gather list processor component within DMACs and intelligent IOPs. The standardized circuit architecture and methods provide a register interface and associated processing capabilities to simplify firmware processing to save and restore context information regarding block transfer operations that are paused and resumed prior to completion. Furthermore, the invention provides for architecture and associated methods for processing of standard scatter/gather list elements by a standardized scatter/gather list processor embedded within DMACs and IOPs. Specifically, as applied in the context of SCSI or Fiber Channel IOPs, the scatter/gather list processor of the present invention simplifies IOP firmware processing to save the current block transfer context on occurrence of a SCSI disconnect and to restore the saved context on occurrence of a SCSI reselect.

Abstract: A method of forming a semiconductor on insulator structure in a monolithic semiconducting substrate with a bulk semiconductor structure. A first portion of a surface of the monolithic semiconducting substrate is recessed without effecting a second portion of the surface of the monolithic semiconducting substrate. An insulator precursor species is implanted beneath the surface of the recessed first portion of the monolithic semiconducting substrate, and a trench is etched around the implanted and recessed first portion of the monolithic semiconducting substrate. The insulator precursor species is activated to form an insulator layer beneath the surface of the recessed first portion of the monolithic semiconducting substrate. The semiconductor on insulator structure is formed in the first portion of the monolithic semiconducting substrate, and the bulk semiconductor structure is formed in the second portion of the monolithic semiconducting substrate.

Abstract: Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method involves providing a substrate having an insulating layer with an opening therein configured to receive an inlaid conducting structure. A copper seed layer is formed on the insulating layer and in the opening. The seed layer is implanted with barrier material ions to form an implanted seed layer. Upon the implanted seed layer is formed a bulk copper-containing layer. The substrate is then annealed so that barrier material ions migrate through the seed layer to an interface between the seed layer and the insulating layer to form a final barrier layer. The barrier material can include palladium, chromium, tantalum, magnesium, and molybdenum.

Abstract: A DVD player or computer with a DVD drive simultaneously presents multiple angles of video on a display. DVD standards provide for formatting and storing video that was filmed from more than one angle. Desired angles are selected, and the DVD player multiplexes between each angle of the playback to decode video frames for each selected angle. The frames for each angle being played back are filtered down to a size that fits into a fragment of the display. Each of the filtered frames are assembled into a single frame that can be presented on the display to simultaneously playback each angle.

Abstract: The present invention is directed to a system and method employing a static logical identifier. In an aspect of the present invention, an input/output interface suitable for communicatively coupling a host with a target device may include at least one port communicatively coupling the input/output interface with a host and at least one port communicatively coupling the input/output interface with a target. A controller is communicatively coupled to the ports. When the controller receives an identifier from the host, the controller generates a logical identifier from the identifier, the logical identifier suitable for being utilized in conjunction with a look-up table to provide access to the target.

Abstract: A circuit combines the outputs of two or more phase locked loops to reduce jitter to a level below that of an individual phase locked loop. A digital version of the circuit uses a majority function to determine the median value of the phase locked loops. An analog version of the circuit averages the outputs of the phase locked loops.

Abstract: A method is presented for self-test and self-repair of a semiconductor memory device. A single built-in self-test (BIST) engine with an extended address range is used to test the entirety of memory (i.e., both redundant and accessible memory portions) as a single array, preferably using a checkerboard bit pattern. An embodiment of the method comprises two stages. In the first stage, faulty rows in each memory portion are identified and their addresses recorded. Known-bad rows in accessible memory are then replaced by known-good redundant rows, and the resulting repaired memory is retested in a second stage. During the second stage, repair of the accessible memory portion is verified, while defects among the redundant portion are ignored. Compared to existing methods, the new method is believed to simplify the interface between the BIST and the built-in self-repair (BISR) circuitry, reduce the overall size of test and repair circuitry, and provide improved test coverage.