Abstract: An apparatus comprising a first stage and a second stage. The first stage may have a first plurality of states connected by a first topology. The second stage may have a second plurality of states connected by a second topology. The second topology may be different from the first topology.

Abstract: Circuits and associated methods for operation thereof for gathering real-time statistical information regarding operation of the arbiter circuit in a particular system application. The real-time statistical information so gathered is useful for off-line analysis by a system designer for determining optimal configuration and parameter values associated with operation of a particular arbiter in a specific system application. In a first exemplary preferred embodiment, a timer circuit associated with the arbiter measures a predetermined period of time during which statistical data is to be gathered. Counter circuits associated with the arbiter count the number of occurrences of events of interest to the designer during the time period measured by the timer circuit. Each counter circuit preferably senses and counts a particular event of interest to the designer.

Abstract: An improved method and design for adjusting clock skew in a wire trace is disclosed. Aspects of the invention include a corrugated pattern wire trace bracketed by a pair of parallel conducting wire frames with wire extensions projecting between the corrugations of the wire trace. The wire frames are connected to a voltage supply. The transmission properties of the wire trace, and thus the degree of clock skew associated with the wire trace, are affected by the number of wire extensions protruding between the corrugations, their degree of penetration, as well as other factors inherent in the design. The present design can achieve the same degree of clock skew with a smaller surface area covered and with fewer resistive losses than with prior art designs.

Abstract: Methods and structure for improving accuracy of a master delay line associated with slave delay lines wherein the master delay line is design utilizing a higher clock frequency then the clock frequency applied to associated slave delay lines. The higher clock frequency applied to the master delay line in accordance with the present invention permits the master delay line to be comprised of fewer delay elements than would be the case for a master delay line using the same basic clock frequency as associated slave delay lines. The lower number of delay elements comprising the master delay line (i.e., the shorter length of the master delay line) helps reduce static phase errors associated with the master delay line inherent in the design, layout and fabrication of a longer delay line.

Abstract: A communications receiver and method are provided for receiving a transmitted signal from a transmission channel having a low-pass filter characteristic. The receiver includes a receiver input for coupling to the channel and a switched capacitor pre-emphasis filter coupled to the receiver input. An analog-to-digital (A/D) converter is coupled to an output of the pre-emphasis filter. An equalizer is coupled to an output of the analog-to-digital converter.

Abstract: An apparatus comprising a data modification circuit and a composite circuit. The data modification circuit may be configured to generate a first and second video component in response to a video data stream. The composite circuit may be configured to present an output graphics stream by interleaving the first and the second video component.

Abstract: According to one embodiment, a method of planarizing of a surface of a semiconductor substrate is provided. A copper layer is inlaid in a dielectric layer of the substrate. The semiconductor substrate is disposed opposite to a polishing pad and relative movement provided between the pad and the substrate. An electrolytic slurry containing abrasive particles is flowed over the substrate or the pad. A voltage is applied between the polishing pad and the substrate to perform electropolishing of the substrate. The rate of chemical mechanical polishing is controlled by the down force applied to a polishing head urging the substrate against the polishing pad.

Abstract: A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.

Abstract: A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric constant spacer layer. Anisotropic etching of the combined layers form spacers surrounding the gate oxide stack.

Abstract: A method of forming an electrically conductive structure on a substrate. An electrically conductive electrode layer is formed on the substrate, and an electrically conductive conduction layer is formed over the electrode layer. The conduction layer is formed by placing the substrate in a plating solution. A first current is applied to the substrate at a first bias and a first density for a first duration. A second current is applied to the substrate at a second bias and a second density for a second duration. The first current and the second current are cyclically applied at a frequency of between about thirty hertz and about one hundred and thirty hertz.

Abstract: The present invention is directed to a system and method of installing additional devices to storage subsystems without disrupting the overall storage system. The present invention may utilize a storage controller which allows testing of devices while the devices are attached to the system by making the devices functionally transparent to the storage system. Further, the present invention may log and report problems discovered during the testing of devices.

Abstract: An over-voltage protected integrated circuit is provided, which includes a discharge node, an input-output pad, a signal trace, which is coupled to the input-output pad, and a pair of back-to-back diodes, which is coupled between the first signal trace and the discharge node.

Abstract: A bonding pad for an integrated circuit, having a conductive base layer. The conductive base layer has slots formed in it, where the slots extend completely through the conductive base layer. An insulating layer is disposed on top of the conductive base layer. The insulating layer protrudes into the slots of the conductive base layer. The insulating layer also includes a low k material. A conductive top layer is disposed on top of the insulating layer.

Abstract: A new relatively high-k gate dielectric gate material comprising calcium oxide will reduce leakage from the silicon substrate to the polysilicon gate, prevent boron penetration in p-channel devices, and reduce electron trapping in the dielectric. The surface of a silicon wafer is saturated with hydroxyl groups. A calcium halide, preferably calcium bromide, is heated to a temperature sufficient to achieve atomic layer deposition, and is transported to the silicon wafer. The calcium halide reacts with the hydroxyl groups. Water is added to carry away the resultant hydrogen halide. Gaseous calcium and water are then added to form a calcium oxide gate dielectric, until the desired thickness has been achieved. In an alternative embodiment of the method, the calcium halide is transported to the silicon wafer to react with the hydroxyl groups, followed by transport of gaseous water to the silicon wafer. These two steps are repeated until the desired thickness has been achieved.

Abstract: The present invention is directed to a system and method for eliminating race conditions in RAID controllers while utilizing a high bandwidth internal architecture for data flow. A remote memory controller of the present invention may ensure that an acknowledge signal is sent only after a memory operation has been actually completed. This may provide for remote direct memory access without coherency problems and data corruption problems while a high bandwidth data flow internal architecture is being utilized.

Abstract: A method for performing backside Photon Emission Microscopy (PEM) on wafer-level failure analysis. The method provides that a die is located by applying reversed-biased voltage to wafer and the backside of the wafer is thereafter observed. The die of interest will illuminate brightly, because of the electron-hole recombination from the reverse-biased protection diode. Such a method is easy to perform and provides a low cost and time-saving way to accurately identify a die and acquire emission.

Abstract: Entries are added or deleted on a search tree starting with a selected vertex on an identified level of the tree. If the level of the selected vertex is the bottom level the entry is inserted to or deleted from the selected vertex. If the level of the selected vertex is not the bottom level, the entries on the child vertices of the selected vertex are redistributed so that the child vertex having a maximal index contains a predetermined number of entries. If the level of the child vertex is the bottom level the entry is inserted to or deleted from the child vertex. Otherwise, the process repeats, using the child and grandchild vertices, until the correct level is reached.

Abstract: Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. A trench is etched in the integrated circuit substrate. A light barrier layer is then formed in the trench such that the light barrier layer at least partially fills the trench to create an isolation structure, the light barrier layer being adapted for absorbing laser light applied during laser thermal processing, thereby preventing damage to the integrated circuit substrate. For instance, the light barrier layer may be a conductive layer such as polysilicon. A dielectric layer is then formed over the isolation structure. The dielectric layer may be adapted for transferring heat generated by the laser thermal processing to the light barrier layer. For instance, the dielectric layer may be formed through oxidation of a top surface of the light barrier layer.

Abstract: In the context of mirror modulation (56, 90, 104) extraction during track seek or jump modes of an optical disc reading device (12), such as a DVD ROM, a mirror averaged level (i.e. the dc level (52) of the RF envelope (34)) is held so that the mirror modulation (90) is seen as a swing below a set mirror rebias level (86) at an output of a mirror amplifier (72), as shown in FIG. 3. With the holding of the dc level (52) by a ground-referred capacitor (302) during seek operation of the device (12), a first input (nin) to the mirror amplifier varies with the mirror modulation, whereas a second input (pin) to the mirror amplifier (72) does not vary. This phenomenon enables the top level of a RFRP signal (82) to be defined by the mirror rebias level (86) and the mirror component swing (during seek operation) to be optimized and always to occur below the mirror rebias level (86).

Abstract: An integrated circuit including an electrically conductive interconnect having a first barrier layer consisting essentially of a diamond film. A seed layer consisting essentially of copper is disposed adjacent the first barrier layer. A conductive layer consisting essentially of copper is disposed adjacent the seed layer.