Patents Assigned to LSI Logic Corporation
  • Simple mechanism for guaranteeing in order read data return on a split transaction bus
    Patent number: 6728816
    Abstract: A circuit that may be used with a split transaction bus. The circuit generally comprises a register logic and a compare logic. The register logic may be configured to (i) present a first identification signal associated with a first slave device to perform a first transaction and (ii) store a second identification signal associated with a second slave device in place of the first identification signal responsive to a ready signal presented by the second slave device. The compare logic may be configured to (i) compare the second identification signal with the first identification signal and (ii) present a back off signal responsive to the compare.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: April 27, 2004
    Assignee: LSI Logic Corporation
    Inventor: Frank Worrell
  • Method of testing the processing of a semiconductor wafer on a CMP apparatus
    Patent number: 6727107
    Abstract: A method of testing the processing of a wafer on a CMP apparatus includes processing a control wafer with the CMP apparatus with a predetermined control consumable combination under a predetermined set of control conditions and generating a control data set which describes the processing of the control wafer with the CMP apparatus, the control data set being based upon the control conditions and a removable rate of the control wafer. The method further includes processing a test wafer with a CMP apparatus with a test consumable combination substantially the same as the control consumable combination under a set of test conditions substantially the same as the set of control conditions. The method further includes generating a test data set which describes the processing of the test wafer with the CMP apparatus.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: April 27, 2004
    Assignee: LSI Logic Corporation
    Inventors: Samuel V. Dunton, Ron Nagahara, Pepito C. Galvez
  • Fabrication of metal contacts for deep-submicron technologies
    Patent number: 6727165
    Abstract: Provided is a process for forming a semiconductor device having salicided contacts. A concentration of metal is formed at the substrate surface by exposing the substrate to a metal plasma. The concentration of metal is then annealed to produce a salicided contact. In a separate embodiment, the metallization plasma and salicide anneal occur in-situ in one process step.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: April 27, 2004
    Assignee: LSI Logic Corporation
    Inventors: Helmut Puchner, Ming-Yi Lee
  • XOR circuit
    Patent number: 6727728
    Abstract: An XOR circuit includes XOR function logic. One advantage of the XOR circuit is that the complements of A and B are not required. The XOR circuit receives an enable signal that disables all the load transistors to eliminate static power dissipation of the XOR circuit and always force the output high when disabled. The output signal of the XOR function logic does not swing rail-to-rail and also has a relatively low drive level. To overcome that, cascade transistor stages are used that have small increments in device sizes, preferably widths, between stages. This allows the fastest rise/fall times at the output of the XOR function logic.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: April 27, 2004
    Assignee: LSI Logic Corporation
    Inventor: Ricky F. Bitting
  • Datapath bitslice technology
    Patent number: 6728936
    Abstract: A method for reducing circuit gate count is disclosed. The method generally comprises the steps of (A) generating a new file from a source file and a parameter file, wherein the source file comprises a first circuit defined in a hardware description language, the new file comprises a second circuit defined in the hardware description language, the parameter file comprises a second clock frequency for the second circuit that is faster than a first clock frequency for the first circuit, and the first circuit is functionally equivalent to the second circuit, (B) generating a first gate count by synthesizing a first design from the source file, (C) generating a second gate count by synthesizing a second design from the new file and (D) generating a statistic by comparing the first gate count to the second gate count.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: April 27, 2004
    Assignee: LSI Logic Corporation
    Inventor: Daniel Watkins
  • Cluster tool reporting system
    Patent number: 6724404
    Abstract: A method for determining an up time of a multi-component tool having discrete elements, where the up time determination is based upon different processes that are to be accomplished in the multi-component tool. The discrete elements of the multi-component tool and the different processes to be accomplished in the multi-component tool are identified. Different tool states for the multi-component tool are determined by setting element states for each of the discrete elements of the multi-component tool. A first possible element state indicates that the discrete element is functional, and a second possible element state indicates that the discrete element is nonfunctional. Possible combinations of the element states of the discrete elements are identified as the different tool states of the multi-component tool.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Thomas C. Hann, Jr., Mark D. Meyer, Theodore O. Meyer
  • Process for reducing defects in copper-filled vias and/or trenches formed in porous low-k dielectric material
    Patent number: 6723653
    Abstract: Removal of rough edges in punctured or ruptured pores on the walls of an opening, such as a via and/or trench opening, in a layer of porous dielectric material, in an integrated circuit structure, is carried out to permit satisfactory lining of all exposed surfaces of the porous dielectric material with a barrier layer which prevents contact between a copper filler and the porous dielectric material, and facilitates filling of the completely lined punctured/ruptured pore with such copper filler to eliminate void formation. The rough edges of the punctured/ruptured pores are removed by an isotropic etch of the exposed walls of the opening. Preferably, the dielectric material in the porous dielectric material is a low k dielectric material.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventor: Yong-Bae Kim
  • Compressed video editor with transition buffer matcher
    Patent number: 6724977
    Abstract: A method and system for determining and recording a minimal ending video buffer verifier fullness at each of a plurality of entry points in a compressed variable bit rate video bit stream.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventor: Elliot N. Linzer
  • Installation and access of a device handler for a peripheral device in a computer
    Patent number: 6725294
    Abstract: In a computer (e.g. an 80×86-compatible personal computer) in which peripheral devices (e.g. hard drives, floppy drives, CD-ROMs, etc.) are accessed through more than one chain of handlers for the peripheral devices (e.g. via interrupts 13h and 40h), an improved device handler for a peripheral device (e.g. a device that complies with the “El Torito” standard) is inserted in both chains (e.g. by “hooking” both interrupts 13h and 40h), so the device handler cannot be bypassed when an access request directed to the device handler is passed through either chain and so the device handler can direct the access request to the next device handler in the correct chain, when appropriate.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Derick G. Moore, Roy W. Wade
  • DEBUG mode for a data bus
    Patent number: 6725306
    Abstract: A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a STATUS_FULL signal when the queue is full of commands and a STATUS_EMPTY signal when the queue is empty. A configuration register provides a DEBUG signal identifying a maintenance status of the slave device. A bus control provides a QUEUE_FULL signal in response to either (1) the STATUS_FULL signal or (2) the DEBUG signal and not the STATUS_EMPTY signal to split further commands or stall the data bus.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Russell B. Stuber, Robert W. Moss, David O. Sluiter
  • Forward error correction apparatus and methods
    Patent number: 6725416
    Abstract: Forward error correction apparatus and methods are described. A forward errro correction method includes: (a) computing syndromes values; (b) computing an erasure location polynomial based upon one or more erasure locations; (c) computing modified syndromes based upon the computed erasure location polynomial and the computed syndrome values; (d) computing coefficients of an error location polynomial based upon the computed modified syndromes; (e) computing a composite error location polynomial based upon the computed coefficients of the error location polynomial; (f) computing a Chien polynomial based upon the computed composite error location polynomial; (g) performing a redundant Chien search on the computed composite error location polynomial to obtain error location values; and (h) evaluating the computed Chien polynomial based upon the error location values to obtain error and erasure values.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventor: Tan C. Dadurian
  • Automatic LAN flow control mechanisms
    Patent number: 6724725
    Abstract: A method operates a media access control device. The method includes (a) detecting the assertion of a flow control condition, (b) generating a PAUSE frame in response to the detection of a flow control condition, the PAUSE frame directing a remote device to PAUSE for a first amount of time, (c) causing the media access device to wait for a second amount of time, the second amount of time being less than or equal to the first amount of time, and (d) generating, upon expiration of the second amount of time and the continued assertion of the flow control condition, an additional PAUSE frame directing a remote device to PAUSE for a first amount of time.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Stephen F. Dreyer, Eric T. West, Donald W. Alderrou
  • Pad conditioning monitor
    Patent number: 6722948
    Abstract: A modification to a chemical mechanical polishing conditioner of a type having a member with a conditioning surface adapted to apply a force to and condition a polishing pad. The conditioner includes at least one sensor disposed within the member, where the at least one sensor is adapted to sense at least one of an amount of the force applied to the polishing pad and a uniformity across the member of the force applied to the polishing pad. In this manner, the force applied by the conditioner to the pad, and the uniformity of the force applied by the conditioner to the pad, can be sensed. These sensed forces can be monitored, reported, and controlled, thus providing a better controlled chemical mechanical polishing process.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventor: Michael J. Berman
  • Amplifier and line driver for broadband communications
    Patent number: 6724219
    Abstract: A line driver for coupling a data transceiver to a transmission line having a load impedance via a transformer with a turns ratio of 1:n includes an input port for receiving an input signal voltage from the data transceiver, an output port for supplying an output signal voltage to the transformer, and an amplifier circuit for amplifying the input signal voltage. The amplifier circuit includes a first output stage, a second output stage coupled to the output port, an output resistor coupled to the first output stage, a feedback path from the first output stage to an input of the amplifier circuit, and a line matching network coupled between the first output stage and the second output stage, for compensating variations in the load impedance, so that a synthesized output impedance of the line driver substantially matches an actual load impedance Z of the transmission line.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Chun-Sup Kim, Ara Bicakci, Cormac S. Conroy, Sang-Soo Lee
  • Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit
    Patent number: 6725389
    Abstract: A method of clock buffer placement for minimizing clock skew includes the steps of (a) constructing a trunk delay model for a plurality of clock cells within a partitioning group, (b) placing a clock buffer at an initial location in the trunk delay model, (c) estimating a clock skew and an insertion delay from the trunk delay model, (d) checking whether the clock skew exceeds a clock skew limit, and (e) if the clock skew exceeds the clock skew limit, then selecting a new location for the clock buffer in the trunk delay model.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Alexander Tetelbaum, Rajiv Kapur
  • Method and apparatus for fibre channel identification and retrieval
    Patent number: 6721320
    Abstract: The invention relates to an improved Fiber Channel data management technique. More specifically, this patent relates to an improved scheme for managing the related data in related frames that form a sequence. This patent also generally relates to the management of multiple, active sequences which are simultaneously in transit on a Fiber Channel. This invention provides a means for efficiently locating the sequence status block associated with an arbitrary Fiber Channel sequence by using the source identifier field, the originator exchange identifier field and/or the sequence identifier fields of a Fiber Channel frame header to construct a hash table lookup search.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: April 13, 2004
    Assignee: LSI Logic Corporation
    Inventors: Timothy E. Hoglund, Louis H. Odenwald, Jr., Elizabeth G. Rodriguez
  • Buffer partitioning for managing multiple data streams
    Patent number: 6721826
    Abstract: The present invention is directed to a buffer partitioning system and a method employing the system to dynamically partition buffer resources among multiple data streams. The buffer partitioning system utilizes context information relating to the streaming data to control the flow of data through the buffer resource. By including a buffer partitioning system, multiple data streams may be more efficiently transferred through buffer resources thus resulting in faster data transfers.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: April 13, 2004
    Assignee: LSI Logic Corporation
    Inventor: Timothy E. Hoglund
  • Method for deriving a word address and byte offset information
    Patent number: 6721869
    Abstract: A method for addressing a particular location of a memory organized as a plurality of words having an odd number (e.g., three) partitions. Upon receiving an address for a particular memory location, address translation circuitry according to the present invention effectively converts the address to a floating point number. The address translation circuitry then divides the received address by three to determine which word of memory—and which byte—is being addressed. In particular, the quotient of the division process provides the word address, while the remainder provides the byte offset. Memory addressed by the present invention may be organized into “words” of varying length. For example, each “word” may be ninety-six bits wide, with partitions of thirty-two bits each. In this embodiment, the remainder of the division process identifies a particular thirty-two bit partition.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: April 13, 2004
    Assignee: LSI Logic Corporation
    Inventor: Gurumani Senthil
  • Algorithm for maintaining maximum streaming performance of mirrored disks
    Patent number: 6721845
    Abstract: A reading algorithm for a set of mirrored disks sends groups of reads to one disk, then sends the next group to the other disk. This provides a more optimal use of disks for sequential reads than previous algorithms. An enhanced version uses snooping of the read requests and switches disks immediately for the read if the requests are not sequential, or within a given number of records of sequential. Additionally, the size of the requests can change the number of requests grouped together in the enhanced version.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: April 13, 2004
    Assignee: LSI Logic Corporation
    Inventors: Roger T. Clegg, Craig Charles McCombs
  • Multi chip module
    Publication number: 20040065951
    Abstract: A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where one each of the heat spreaders is associated with one each of the integrated circuits. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.
    Type: Application
    Filed: August 11, 2003
    Publication date: April 8, 2004
    Applicant: LSI Logic Corporation
    Inventors: Leah M. Miller, Kishor Desai