Abstract: A method of processing a semiconductor wafer and an associated semiconductor wafer arrangement which inhibits “punch through” and increases the yield of functional semiconductor wafers during the fabrication thereof is disclosed.

Abstract: A semiconductor device wherein some parts of a circuit are disposed on Si—Ge regions and others are implemented in Silicon substrate regions of the chip. The Si—Ge region provides that carrier flow is forced to the surface channel region which helps reduce short channel effects. A method of making such a semiconductor device is also provided and includes steps of forming a thermal oxide layer on a Silicon substrate, masking at least a portion of the thermal oxide layer, removing at least a portion of the thermal oxide layer in order to expose a portion of the Silicon substrate, epitaxially growing an Si—Ge layer on the exposed portion of the Silicon substrate, epitaxially growing a Silicon layer on the Si—Ge layer, and continuing manufacture of the device by forming a circuit on the Si—Ge regions and non-Si—Ge regions of the semiconductor device.

Abstract: A method for making a heterojunction bipolar transistor on an insulated semiconductor substrate. A highly doped subcollector is formed on an insulated substrate. A lightly doped collector is formed adjacent to and in direct contact with the subcollector. An extrinsic base film stack is deposited on the lightly doped collector. A collector base S and base emitter junction window are etched in the extrinsic base film stack. A doped semiconductor intrinsic base is formed in the junction window. A self aligning base emitter spacer is formed and etched in the junction window and the emitter material is deposited and etched in the junction window. Oxide spacers are deposited and etched adjacent walls of the emitter material. The extrinsic base is defined and conductors are deposited on the device to provide a heterojunction bipolar transistor having improved resistance and capacitance characteristics.

Abstract: A technique is described for enabling routing of metallisation wires over sensitive cells of an integrated circuit by means of a global router after the cell circuits have been designed. At least one cell includes dedicated route paths (32, 36, 40, 46) as part of the cell design. The paths may include alternative paths (32 and 36), and concurrently usable paths (40 and 46). By including the routes as part of the cell design, the subsequent problems of a global routing tool routing wires over sensitive areas of the cell can be avoided, and the number of wire routes can be controlled. The global router operates by detecting whether dedicated routes are provided and, if so, identifying the entry/exit points for routes to be used.

Abstract: A process for re-designing IC chips by altering the positions of cells from a first to a second IC chip layout. An x,y grid is established for the first and second IC layouts such that each cell has identifying x,y coordinates in the first layout. Columns are established in the second layout based on the bounds of the second layout in the x-direction. The cells are sorted to the columns in the order of cell x-coordinates to establish new x-coordinates for each cell based on the x-coordinates of the respective column. The cells are sorted in each column to establish y-coordinates for each cell based on the height of the cells in the column and the height of the column.

Abstract: A video decoding system includes an embedded microcontroller that provides memory arbitration in addition to processing and control functions. The microcontroller architecture provides a first-in, first-out (FIFO) queue for storing memory access instructions and a processing logic for executing software instructions. The microcontroller processing logic determines which components within the decoding system need access to memory and stores a sequence of memory access instructions into the FIFO queue. Each memory access instruction is associated with one decoder component. When main memory becomes available, a memory access instruction is dequeued from the FIFO and transmitted to the associated decoder component, which is then permitted to access memory. The microcontroller receives indicator signals from the decoder components that indicate when the decoder components have finished accessing memory and, thus, when the memory device is available for subsequent transactions.

Abstract: A method and apparatus for performing efficient reseeks in an optical storage device. As data sectors are read by the optical storage device, address information corresponding to sectors being processed by the optical storage device is stored in a stack. The stack may be composed of shift registers that shift the address information of new sectors down the stack as they are read. When an interrupt occurs, a selector determines which stack location contains address information for the sector being processed, and transfers the address information to a register. The address information is held in the register until it is accessed by a microprocessor. The microprocessor uses the address information to determine a reseek location, and causes the sector being processed to be read again.

Abstract: Persistent reservations may be processed on an as-needed basis after a power cycle sequence. A computer storage device may have persistent reservations for various volumes that are to be deleted after a power cycle but before accepting any reservation I/O requests for those volumes. After a start up sequence, the device comes on-line prior to deleting the required registrations. Prior to the first reservation I/O request for the particular volume, the registrations are processed for that volume and the necessary registrations are deleted.

Abstract: The present invention is directed to a system and method for effective approximation of smooth functions. In an aspect of the present invention, a method for approximating a smooth function for implementation in an integrated circuit design includes receiving a function f for computation with an accuracy of m bits by an integrated circuit. The function is computed based on an operator with one more output than the accuracy of m bits and a value of f′ is determined by choosing from one of the at least two numbers computed utilizing the operator with one more output. The value may be chosen based on complexity issues in the construction of a binary decision diagram for use in designing the integrated circuit.

Abstract: A method of testing a floor plan for an integrated circuit prior to resynthesis includes attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has an unreachable pin; and if the least-penalty path is constructed, then attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has a bottleneck.

Abstract: The present invention is directed to a system and method for providing an overlap remover manager. A method for removing overlaps in a circuit design for an integrated circuit may include initiating an overlap remover manager, wherein the overlap remover manager is suitable for moving cells of an integrated circuit design to remove cell overlaps. A search for critical wires is performed and a determination is made of which violated moves of cells caused at least one critical wire. A determined violated move of the cells is rolled back and the overlap remover manager employed to remove overlaps between rolled back cells.

Abstract: A system, apparatus and/or method is provided for fabricating an integrated capacitor during the fabrication of a transistor employing chemical mechanical polishing of a gate electrode of the transistor. Components of the integrated capacitor, particularly the lower electrode of a parallel plate capacitor in one form thereof, and an outer plate of a cylindrical-like capacitor in another form thereof, are defined by the polish stop layer during chemical mechanical polishing (CMP) of a gate of the transistor. According to an aspect of the subject invention, the polish stop layer may be an oxide or a nitride.

Abstract: A method for adjusting preliminary feature position characteristics of a preliminary mask pattern on a mask to produce a desired etch pattern on a substrate having desired feature position characteristics.

Abstract: The present invention provides a method for reliability testing leakage characteristics in an electronic circuit, and a testing device for accomplishing the same. In an advantageous embodiment, the method includes dividing conductors of an electronic circuit into at least first and second noninterleaved regions having at least two conductors each. The method further includes forming conductor nets by electrically connecting ones of the at least two conductors of the first region to ones of the at least two conductors of the second region then testing for electrical leakage in the conductor nets.

Abstract: Accurate models of the contact region of an integrated circuit resistor are created in a single function. The function incorporates many contact geometries into a single function that cannot otherwise be represented by a closed form solution. A method of creating the function uses regression over the simulation results for many combinations of input variables. The function may use the contact resistance, metal trace resistance, and resistive area resistance as inputs to calculate the resistor contact region resistance.

Abstract: A serial data communication receiver includes a serial data input and first and second sets of data capture latches, which are coupled to the serial data input and have first and second recovered data outputs, respectively. One of the sets is designated as a master set and the other a slave set. Each data capture latch has a respective independently adjustable offset voltage. An offset adjustment control circuit varies the respective offset voltage over a range of offset voltage values for each of the data capture latches in the slave set while comparing the first and second recovered data outputs to produce an error output. The control circuit then sets each of the respective offset voltages in the slave set to one of the offset voltage values based on the error output.

Abstract: A test package for electromigration testing includes a die having a plurality of I/O pads formed on a metal layer, a plurality of traces formed on the die electrically connecting adjacent pairs of the I/O pads, a plurality of bumped interconnects formed on the I/O pads, and a substrate having a plurality of bump-to-bump interconnects formed on a top surface of the substrate adjacent to the die wherein the plurality of bump-to-bump interconnects is electrically coupled to the plurality of bumped interconnects so that the plurality of bumped interconnects is connected in series.

Abstract: Control signals of an I/O or peripheral bus are sensed during cycles of the bus and information describing bus phases of the signals is derived by sensing the control signals and is stored in a register. During a sampling time period, a processor reads the bus phase information from the register and computes bus activity information by using the bus phase information. The computed bus information is continuously updated and displayed to reflect actual communication activity on the bus occurring substantially in real-time.

Abstract: Provided is a chemical mechanical polishing pad which as capable of draining used slurry from the polishing pad surface through the pad. Chemical mechanical polishing pads according to preferred embodiments of the present invention have slurry drain holes to drain slurry from the pad surface. In various preferred embodiments, the drain holes are combined with drain grooves in the pad surface and/or the pad/pad backing or pad/platen interface to provide a path for used slurry to exit the pad. The invention also provides a method of conducting CMP using through-pad slurry drainage.

Abstract: A system for receiving transaction requests from a plurality of data access devices, coupling them to a shared memory having an input queue and identifying each completed transaction with the requesting device. The system includes a controller for receiving the requests and selectively coupling them to a shared memory input queue. A first-in-first-out identification memory stores a requesting device identifier which the controller uses to route transaction completion control signals and data back to the device which requested the transaction.