Abstract: A method and apparatus are provided for estimating gate leakage of an integrated circuit design having a plurality of transistors. The method and apparatus simulate an operating state of the integrated circuit design and estimate the gate leakage as a function of the states of the transistors in response to the simulated operating state.

Abstract: A probe structure with a connector connecting the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. A back side layer is connected to the connector. A probe side layer with contacts is sandwiched with the back side layer in a layered substrate. The probe side layer has a centrally disposed signal contact and surrounding ground contacts. A conductive layer is disposed between the back side layer and the probe side layer. The conductive layer is connected to the ground conductor of the connector and to the ground contacts of the probe side layer contacts. A via extends from the back side layer to the probe side layer. The via is connected to the signal conductor of the connector, and is also connected to the centrally disposed signal contact of the probe side layer contacts. The via does not make connection with the conductive layer.

Abstract: A circuit generally comprising a tank circuit and an inverter circuit. The tank circuit may be configured to generate a first signal having a frequency of oscillation in response to a second signal. The inverter circuit may be configured to (i) generate the second signal in response to inverting the first signal and (ii) adjust a delay in generating the second signal in response to an input signal to change the frequency of oscillation.

Abstract: Isochronous data transfers guarantee data packets are received at a particular frequency and within a prespecified jitter-tolerance. Asynchronous data transfers guarantee data integrity by allowing missed or errant packets to be resent as many times as needed until an error-free packet may be reconstructed at the receiver. Isochronous transfers address real-time needs but do not address the data integrity issue. Asynchronous transfers address the data integrity issue but cannot guarantee error-free data packets will be available so as to meet a real-time constraint. The present invention provides method and apparatus enable isochronous data transfers with improved data integrity. Various link layer and transaction layer mechanisms are taught. An embodiment involving the IEEE 1394 bus specification is addressed in detail.

Abstract: An apparatus comprising a translator circuit and a cache. The translator circuit may be configured to (i) translate one or more first instruction codes of a first instruction set into second instruction codes of a second instruction set, (ii) present the second instruction codes to a processor, and (iii) allow interrupts to the processor to be handled seamlessly.

Abstract: A method of detecting presence of a polishing slurry on a semiconductor wafer subsequent to polishing of the wafer includes the step of adding a chemical marker to the polishing slurry. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. In addition, the method includes the step of applying the polishing slurry to the first side of the wafer during the polishing step. Moreover, the method includes the step of ceasing the polishing step when the wafer has been polished to a predetermined level. Yet further, the method includes the step of directing incident electromagnetic radiation onto the wafer subsequent to the ceasing step. The method also includes the step of detecting a physical characteristic of resultant electromagnetic radiation which is produced in response to the incident electromagnetic radiation being directed onto the wafer.

Abstract: A controller generally comprising a DMA engine, a processor, and a circuit. The DMA engine may be configured to copy from a system memory to a local memory. The processor may be configured to process a message written in the local memory. The circuit may operate independently of the processor. The circuit may be configured to (i) monitor writes to the local memory for the message having a first pointer and (ii) program the DMA engine to copy a first buffer identified by the first pointer in response to the first pointer having a non-null value.

Abstract: A clock recovery mechanism for an ATM receiver recovers a service (source) clock transmitted over an ATM network. The mechanism includes an input for receiving an SRTS from the ATM network, a local SRTS generator for locally generating an SRTS, a comparator for comparing a received SRTS and a locally generated SRTS and a recovered service clock generator responsive to an output of the comparator for generating the recovered service clock and for controlling the local SRTS generator. The locally generated SRTS is compared directly with the received SRTS. The local SRTS is generated using the same method as used to generate the transmitted SRTS, that is using the network clock fnx and a locally generated clock, at frequency fs. The difference between the locally generated SRTS and the received SRTS can be expressed directly in a number of fnx pulse clocks to be added or removed to the generated fs clock. Thus a service clock can be recovered at a receiver location using SRTSs by means of a digital technique.

Abstract: A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises one of one or more layers of dielectric material formed over raised portions of the underlying integrated circuit structure. Prior to the planarization step, a removable mask is formed over such one or more dielectric layers formed over raised portions of the integrated circuit structure. Openings are formed in the mask to expose a portion of the upper surface of the one or more dielectric layers in the region over at least some of these raised portions of the integrated circuit structure. Exposed portions of the underlying one or more dielectric layers are then etched through such openings in the mask to reduce the overall amount of the one or more dielectric layers overlying such raised portions of the integrated circuit structure.

Abstract: An apparatus comprising a memory, a write pointer, a read pointer and a control circuit. The memory may have a plurality of memory locations accessed by a plurality of addresses. The write pointer may be configured to write data to the memory in response to a sequence of write addresses generated in response to a first control signal. The read pointer may be configured to read data from the memory in response to a sequence of read addresses generated in response to a second control signal. The control circuit may be configured to generate (i) the first control signal, and (ii) the second control signal. The order data is read from said memory may comprise a de-interleaved pattern with respect to the order the data is written to the memory.

Abstract: A cell for inclusion in a cell library used in designing integrated circuits. The cell includes a signal processing circuit and a buffer circuit for buffering a signal external to an integrated circuit in which the cell is to be included. The cell also includes layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit. The invention is also directed to a method for performing layout and routing during design of an integrated circuit, in which cells are obtained from a cell library, the obtained cells are laid out on an integrated circuit die, interconnections are routed between the cells.

Abstract: For use in a processor having an instruction cache, an instruction memory and an external synchronous memory, a memory management mechanism, a method of managing memory and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes an external memory request abort circuit coupled to the external synchronous memory and an instruction cache invalidator associated with the external memory request abort circuit. In this embodiment, the external memory request abort circuit aborts a request to load an instruction from the external synchronous memory before the information is loaded into the instruction cache. Additionally, the instruction cache invalidator invalidates the instruction cache when address spaces of the instruction memory and the external synchronous memory overlap and the processor switches between the instruction memory and the external synchronous memory.

Abstract: A memory controller includes an input command decoder circuit for generating an input command, a state machine controller coupled to receive the input command from the input command decoder circuit and generate a state machine input instruction therefrom, a state machine array comprised of a plurality of state machines coupled to receive the input command and state machine input instructions from the state machine controller and to generate state machine output instructions therefrom, and an output command decoder circuit for receiving a state machine output command and generating an output command therefrom for transmission to a memory, associated with the memory controller, comprised of a plurality of memory banks. A first state machine execute a state machine input instruction transmitted, with the input conunand, to all state machines if a memory address contained within the input command corresponds to an address for a corresponding memory bank.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: A reticle includes multiple different layer patterns selected from a group comprising same circuit layer patterns and different circuit layer patterns. The layer patterns are positioned on the reticle within borders and within a portion of a defined x by y array on the reticle. The reticle is used to produce an integrated circuit of a single design or integrated circuits of multiple designs.

Abstract: An integrated circuit having circuit structures, including at least one of logic elements and memory elements. A core is disposed at an interior portion of the integrated circuit. The core contains core power contacts and core ground contacts for providing electrical power to the circuit structures during functional operation of the integrated circuit. A peripheral is disposed at an edge portion of the integrated circuit. The peripheral contains signal contacts for sending and receiving electrical signals between the circuit structures and external circuitry. The peripheral also has peripheral power contacts and peripheral ground contacts for providing electrical power to the circuit structures during testing of the integrated circuit. The peripheral power contacts are redundant to at least some of the core power contacts, and the peripheral ground contacts are redundant to at least some of the core power contacts.

Abstract: A design which allows burn-in of DRAM's at the wafer level, as opposed to in die form or after the package has been assembled. The DRAM dies on the wafer are IEE1149.1 (JTAG) compliant, and the TDO pad of each die is connected to the TDI pad of the next die. The dies are arranged in rows, and each die in a given row is daisy chained to the next die in the row. The last die in the row is daisy chained to the first die in the next row. Additionally, the TMS and TCK pads of the dies are connected in parallel, such as via metal lines running along the scribe area of the wafer. The DRAM dies on the wafer are also connected to power busses along the scribe area so that the individual dies can be powered.

Abstract: As technology in the semiconductor industry advances, semiconductor devices decrease in size to become faster and less expensive per function. Smaller semiconductor devices, particularly MOSFETs, are increasingly sensitive to Electrostatic Discharge (ESD). ESD can either destroy or permanently damage a semiconductor device. Embodiments of the present invention assist in preventing ESD damage to semiconductor devices. An embodiment of the present invention utilizes a diode connected to the substrate terminal of a MOSFET. Under normal operation up to the maximum operating voltage, the diode and MOS devices are open and do not conduct. The diode triggers when an ESD pulse causes the reverse breakdown voltage of the diode to be exceeded. The resultant current switches a connected MOS device, operating in bipolar mode, to dissipate the damaging ESD pulse. The ESD pulse is shunted to ground, thereby avoiding damage to the rest of the device.

Abstract: A method for providing under bump metallization on a substrate. Trenches are formed in the substrate, and a layer of first electrically conductive material is formed over the substrate. The layer of the first electrically conductive material substantially fills the trenches and substantially covers the substrate between the trenches in a contiguous sheet. The layer of the first electrically conductive material is thinned to an end point where the layer of the first electrically conductive material is substantially reduced in thickness, but still forms the contiguous sheet between the trenches. A layer of photoresist is applied over the layer of the first electrically conductive material to define openings. A second electrically conductive material is deposited into the openings. The photoresist layer is removed, and the layer of the first electrically conductive material in the contiguous sheet between the trenches is removed to isolate the first electrically conductive material in the trenches.

Abstract: A static random access element is comprised of three transistors and two resistors. Two transistors have their gates and drains cross connected to the respective drains and gates of the opposite transistor. Two resistors make the connection from a power supply to the drains of each of the two transistors. A first control line is connected at the junction of the two resistors. The source of a third transistor is connected to the gate of one of the first transistors and the drain of the third transistor is connected to a second control line and a power supply. The gate of the third transistor is connected to a third control line. The three transistor SRAM cell is more compact and requires fewer control lines than typical SRAM cells.