Abstract: A system for receiving transaction requests from a plurality of data access devices, coupling them to a shared memory having an input queue and identifying each completed transaction with the requesting device. The system includes a controller for receiving the requests and selectively coupling them to a shared memory input queue. A first-in-first-out identification memory stores a requesting device identifier which the controller uses to route transaction completion control signals and data back to the device which requested the transaction.

Abstract: The present invention is directed to a system and method employing a dynamic logical identifier. In an aspect of the present invention, a method for accessing data utilizing an input/output interface may include providing an identifier for accessing a target device by a host and generating a logical identifier from the obtained identifier by the host. The logical identifier is transferred to an input/output interface and a look-up table is accessed utilizing the logical identifier by an input/output interface controller. The look-up table is included on the input/output interface, wherein the look-up table provides access between the input/output interface and the target device so as to enable the host to access the target device.

Abstract: A method of debugging an IKOS model. The method includes mapping information contained in either a .pin or .lde file or both into corresponding files which are more user-friendly, readable and editable. Preferably, a .v file which is readable to create a schematic view of the cell is also created and the schematic view can be viewed and analyzed. Then, the one or more user-friendly files which have been created can be read and edited, and the .pin and/or the .lde file is re-created. Then, a tool is used to analyze the .pin and .lde files again and determine whether there is a functional or timing failure.

Abstract: A novel method and apparatus for encoding input data at a faster rate provides error detection, clock recovery, and reduction of spectral components near DC, and is capable of encoding data while embedding error detection information simultaneously. This encoding scheme may encode all input data in parallel while simultaneously embedding error detection information to quickly and properly encode input data.

Abstract: A mirrored data storage system utilizes a first host device and a local storage device for primary data storage and a second host device and a remote storage device for mirrored, fail-over storage on behalf of client devices. At periodic intervals (called checkpoints), the first host device initiates data synchronization between itself and the two storage devices and issues checkpoint information to ensure that each device maintains information for a common stable storage state. The local storage device synchronizes its stored data and forwards the checkpoint information to the remote storage device. The remote storage device maintains a copy (called a snapshot) of the data at the common stable storage state. Given the snapshot and the checkpoint information, the remote storage device can restore itself to the common stable storage state in the event of a failure of the first host device and/or the local storage device.

Abstract: A “Wrapper” system and method are presented for integrating built-in self-test (BIST) and built-in self-repair (BISR) functions in a semiconductor memory device. The wrapper reduces the usual dependency of BISR circuitry on the BIST design, so that modifications and enhancements to the BIST may be made without requiring significant changes to the BISR. A generic BIST engine with an extended address range (spanning both the accessible and the redundant rows) is used to test the entirety of memory as a single array, preferably using a checkerboard bit pattern. The memory is tested in two stages, using the same BIST algorithm. In the first stage, faulty rows in each memory portion are identified and their addresses recorded. At the end of the first stage a repair process allocates good redundant rows to replace faulty accessible rows. During the second stage, repair of the accessible memory portion is verified, while defects among the redundant portion are ignored.

Abstract: A circuit embodied in an integrated circuit is characterized by an architecture having a minimal depth defined by a recursive expansion of output functions h_n=OR(h_k, AND(v_k, h_{n−k})) and v_n=AND(v_k, v{n−k}), where k=F_l and n−k=F_{l−1}, satisfies F_l<n=F_{l+1}, {F_l} is a Fibonacci series and n is the number of bits of an input to the circuit. In one form, the circuit is a comparator having output functions h_n and v_n that depend from input functions U[i]=AND(NOT(A[i]), B[i]) and V[i]=OR(NOT(A[i]), B[i]), where A[i] and B[i] are inputs to the comparator, and functions h_n, v_n defined as h_n=h_n(U[0], U[1], V[1], . . . , U[n−1], V[n−1])=OR(U[n−1], AND(V[n−1], U[n−2]), . . .

Abstract: An apparatus comprising a circuit configured to (i) translate one or more instruction codes of a first instruction set into a sequence of instruction codes of a second instruction set and (ii) present the sequence of instruction codes of the second instruction set in response to a predetermined number of addresses.

Abstract: A double data rate (DDR) circuit for testing of a high speed DDR interface using single clock edge triggered tester data. The DDR testing circuit includes a first register, a second register, and a multiplexer (MUX). A clock signal is fed to the first register and the MUX. The inverse of the clock signal is fed to the second register. A tester data signal is fed to the first register which generates a latched tester data signal which is fed to the MUX. The inverse of the latched tester data signal is fed to the second register which generates a transformed tester data signal which is fed to the MUX. The MUX generates a combination of the latched tester data signal and the transformed tester data signal for transmission as an applied test data signal. The resulting applied test data signal has double the data rate of the tester data signal upon which it is based.

Abstract: A first-in-first-out (“FIFO”) buffer is provided for buffering communication data. The FIFO buffer includes a write port having a data input, an end-of-frame input and a write control input, a read port having a data output, an end-of-frame output and a read control input, and a plurality of storage locations. A write end-of-frame counter is coupled to the write port and has a write count output, which increments as a function of the end-of-frame input and the write control input. A read end-of-frame counter is coupled to the read port and has a read count output, which increments as a function of the end-of-frame output and the read control input. A comparator has a first compare input coupled to the write count output, a second compare input coupled to the read count output and a compare output indicating whether there is a data frame stored in the plurality of storage locations.

Abstract: A two layer PBGA which includes a metal ground plane at its bottom layer. The ground plane is preferably a metal plane which is connected to ground through a metal connection to a ball pad at the center of the package and a ball pad proximate the edge of the package. The ground plane is voided around the signal and power balls, via and “dog bones”. The PBGA is configured such that the ground plane serves effectively the same function as the second layer ground plane in a conventional four layer PBGA. The PBGA provides a cheaper alternative to the generally more expensive four layer PBGA, and provides better cross talk performance (especially for high frequency signaling) as well as better thermal performance as a result of having more metal at the bottom layer of the package.

Abstract: A bridge for connecting a DSP to an ASIC on-chip bus as a master on the bus. The bridge includes a DSP instruction unit master interface and a DSP data unit master interface to convert DSP instruction unit and data unit external signals into bus protocol signals. An arbiter is provided to receive the signals from the two DSP interfaces and selectively pass the signals to a generic bus master which couples the signals to the on-chip bus. A synchronization unit is provided to insure alignment of positive clock transitions between the different clock frequencies of the ASIC and the DSP and to buffer signals as needed. The generic bus master couples signals from the arbiter and the synchronization unit to the ASIC bus in full compliance with the bus protocol.

Abstract: The present invention is directed to a silicon carbide anti-reflective coating (ARC) and a silicon oxycarbide ARC. Another embodiment is directed to a silicon oxycarbide ARC that is treated with oxygen plasma. The invention includes method embodiments for forming silicon carbide layers and silicon oxycarbide layers as ARC's on a semiconductor substrate surface. Particularly, the methods include introducing methyl silane materials into a process chamber where they are ignited as plasma and deposited onto the substrate surface as silicon carbide. Another method includes introducing methyl silane precursor materials with an inert carrier gas into the process chamber with oxygen. These materials are ignited into a plasma, and silicon oxycarbide material is deposited onto the substrate. By regulating the oxygen flow rate, the optical properties of the silicon oxycarbide layer can be adjusted. In another embodiment, the silicon oxycarbide layer can be treated with oxygen plasma.

Abstract: When designing an electronic circuit to be implemented on an integrated circuit die which includes several metal layers, a technology-independent description of a system is generated, the technology-independent description specifying a signal and a selected metal layer for the signal. Also, an electronic circuit description of a system is synthesized from a technology-independent description of the system. Specifically, a technology-independent description of the system is input, the technology-independent description specifying a signal and a metal layer attribute for the signal. Electronic components are selected from a library based on the technology-independent description and interconnections between the electronic components are specified. A metal layer is then specified for an interconnection corresponding to the signal specified in the technology-independent description based on the metal layer attribute specified in the technology-independent description.

Abstract: A logic analyzer or a bus analyzer may be used to capture data from a source computer system to diagnose a problem arising in the source computer system. In many cases the problem can be traced to a particular hardware/software subsystem. Quite often, a customer of the manufacturer of the hardware/software subsystem maintains the source computer system. In the manufacturer's facilities is a reference system operated by a technician or engineer responsible to test and support the hardware/software subsystem. The source computer system and the reference system thus may involve different hardware and software configurations and possibly even different operating systems. The present invention provides a system and a method to allow data captured in a source computer system to be replayed in the remote reference system so as to recreate a captured event or analyze performance.

Abstract: A method for changing the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively, utilizes the memory compiler for setting the number of core cells used for driving a self time column of the memory.

Abstract: A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate.

Abstract: A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material.

Abstract: A circuit generally comprising a queue having an input and an output. The queue may be used to buffer memory requests generated by a processor to access a memory. The input may be configured to receive a plurality of memory requests. The memory requests may include a plurality of write requests and a plurality of read requests. The output may be configured to present the memory requests. The queue may be configured to (i) store the memory requests received at the input in an arrival order, (ii) rearrange the memory requests by propagating each read request ahead of each write request to establish a presentation order, and (iii) present the memory requests at the output in the presentation order.

Abstract: The invention may relate to a digital to analog converter. The digital to analog converter may comprise a plurality of controllable current sources and a control circuit. The plurality of controllable current sources may include a first and a second controllable current source. Each of the plurality of controllable current sources may be controllable between a first state and a second state. The control circuit may be coupled to the plurality of controllable current sources. The control circuit may be configured to control digital to analog conversion at a sampling interval. The control circuit may be configured to control a first state transition of the first controllable current source at a timing in the sampling interval different from a second state transition of the second controllable current source.