Abstract: A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer.

Abstract: A method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the isolation punchthrough tolerance and the SER immunity of the device. The additional well tub is deposited to a depth that is shallower than the standard well tub. The additional well tub is deposited using an ion implantation process using the same mask set as that used for the threshold voltage adjustment deposition. Thus, no additional mask layer is required to deposit the additional well tub, and the all of the expenses normally associated with an additional mask layer are avoided.

Abstract: A circuit for converting data between communication protocols at different levels of a protocol stack. The circuit generally comprises a first processor and a second processor. The first processor may be configured to convert the data between a first communication protocol and a second communication protocol. The first processor may have a plurality of first rows each having at least one first block each configured to process a portion of the data. At least one of the first rows may have a plurality of the first blocks. The second processor may be configured to convert the data between the second communication protocol and a third communication protocol. The second processor may have a plurality of second rows each having at least one second block each configured to process a portion of the data. At least one of the second rows may have a plurality of the second blocks.

Abstract: Methods for calculating delays for cells in ASICs are disclosed. In the present invention, delays are computed by considering not only the process (P), voltage (V), temperature (T) but also input ramptime (R) and output load or fanout (F) of the cells by fitting the delay at four corner points for derated PVT condition into a non-linear equation which is a function of P, V, T, R and F. Thus, the delay is a five dimensional characterization, and the characterization is split into (P,V,T) characterization and (R,T) characterization to reduce the characterization time and resources. The present invention provides for accurate calculation of delays for cells in ASICs.

Abstract: A method of compensating for initial signal interference exhibited by a differential transmission line includes the step of determining whether the differential transmission line has been at a first differential voltage state for at least a first predetermined time period. The method also includes the step of transmitting a first data bit across the differential transmission line by impressing a first differential voltage having a first magnitude upon the differential voltage line in order to drive the differential transmission line from the first differential voltage state to a second differential voltage state if the determining step determines that the differential transmission line has not been at the first differential voltage state for at least the first predetermined time period.

Abstract: Process voltage temperature compensation are used for a bus driver; specifically, a PCI-X 2.0 DDR Standard bus driver. Performance is improved by enhancing the speed of the PCI-X buffer by removing the statically controlled gate stages and providing for output signal slew control by dual use of on-resistance of signal pass transistors. Although directed to PCI-X technology, this circuitry may also be used in SCCI, controlled impedance drivers, and other buffers, where short propagation delay and signal integrity are of concern.

Abstract: A process is described for planarizing an isolation structure in a substrate. The process includes depositing a pad protective material over an upper surface of the substrate, and selectively removing portions of the pad protective material to expose portions of the substrate and to form sidewalls in the pad protective material. A trench is formed in the exposed portions of the substrate, and a trench fill material is deposited in the trench and over the pad protective material. A trench protective material is deposited over the trench fill material and in contact with the sidewalls of the pad protective material, such that the pad protective material and portions of the trench protective material together form a continuous protective material layer. Portions of the trench protective material and the trench fill material are selectively removed down to the level of the upper surface of the pad protective material.

Abstract: A method and apparatus are provided for addressing a memory device. The apparatus receives a system address from a memory access device having an endianess. The system address has a word address bit corresponding to word boundaries within the memory device. The apparatus selectively inverts the word address bit as a function of the endianess of the memory access device to produce a selectively modified system address. The apparatus then accesses a memory location with the memory device based on the selectively modified system address.

Abstract: A video filter unit is described which is implemented as a three-stage filter comprising a vertical filter, a horizontal decimation filter, and a horizontal interpolation filter. The three stages of the filter unit preferably connect serially with the vertical filter comprising the input first stage, the horizontal decimation filter comprising the second stage and the horizontal interpolation filter comprising the third stage which provides the output filtered image from the filter unit. As such, the video data to be filtered is provided to the vertical filter which provides its output to the horizontal decimation filter. After horizontal decimation, which can be disabled if desired (i.e., no horizontal decimation), the video data is then horizontally interpolated. The horizontal interpolation filter stage can also be disabled if desired. The vertical filter can be configured to operate either as a decimation filter or an interpolation filter.

Abstract: Structure and methods for reduced latency in calculating an error signal based on the output of a Viterbi detector. Certain partial terms of the error signal are precomputed before the final output of the Viterbi detector is determined. The precomputed terms are used to determine the error in fewer clock cycles once the Viterbi output is fully determined. In one exemplary embodiment, the final Viterbi output is used as an input to a multiplexer that selects a precomputed error. In addition to calculating an error signal, a level signal may be precomputed as well so that the level signal is available more quickly after the output of the Viterbi detector is fully determined.

Abstract: A self-time circuit and method are presented for reducing the write cycle time in semiconductor memory. A “dummy” memory cell having the same timing requirements as the functional cells, and associated write logic are added to the standard circuitry of the memory device. The dummy write cell receives the same control signals used to write data to the functional cells of the memory, and is configured to issue a completion signal when a write access is concluded, causing the write cycle to be terminated. The circuit and method disclosed herein thus permit write cycle time to be reduced to the lowest practical value, independently of the read cycle time. This potentially increases the overall operating speed of the memory device. The circuit and method disclosed herein are adaptable to the most common types of memory devices, such as SRAM, DRAM and CAM.

Abstract: An apparatus comprising a processor and an interface. The processor may be configured to support system-on-chip debugging. The interface circuit may be coupled to the processor and configured to interface with an external bus. Reading and writing commands of the processor may be integrated with the system-on-chip debugging.

Abstract: A substrate for electrically connecting to an integrated circuit, where the integrated circuit has differential pairs of signals that are associated with differential pairs of integrated circuit contacts. Differential pairs of substrate contacts are disposed on a first substrate layer in alignment with the differential pairs of integrated circuit contacts. Differential pairs of vias are also disposed on the first substrate layer, and extend to at least one underlying substrate layer. The differential pairs of vias make electrical connections with the differential pairs of substrate contacts. Each via within a given one of the differential pairs of vias is disposed within a column with each other on the first substrate layer. The columns for each of the differential pairs of vias are in a substantially parallel arrangement one with another. Differential pairs of traces are disposed on the at least one underlying substrate layer.

Abstract: An optical waveguide extends vertically within the interior of an IC-like structure to route optical signals between horizontal waveguides in different layers of horizontal optical interconnects. A light reflecting structure is positioned at the intersection of the horizontal and vertical waveguides to reflect the light. Multiple horizontal waveguides may join the vertical waveguide at a common intersection, to form a beam splitter or a beam combiner. Optical signals from one horizontal waveguide are diverted within the IC-like structure into another horizontal or vertical waveguide. The waveguide is formed with a light reflective structure at an intersection of the horizontal and vertical waveguides, and the waveguide is completed using damascene fabrication techniques.

Abstract: Provided is a technique for designing an integrated circuit die which includes a semiconductor layer, a primary metal layer, a horizontal metal layer and a vertical metal layer. Electronic components are laid out on the semiconductor layer, and a primary power distribution network for distributing power to the electronic components is laid out on the primary metal layer. Then, a uniform trunk width is calculated for all trunks in a power mesh based on a desired maximum voltage drop for the generated electronic component layout. Finally, horizontal power trunks are laid out on the horizontal metal layer and vertical power trunks are laid out on the vertical metal layer using the calculated uniform trunk width, so as to form the power mesh, and an electrical connection is specified between the power mesh and the primary power distribution network.

Abstract: A method of clock buffer placement for minimizing clock skew for an integrated circuit includes the steps of (a) finding an ideal location for a clock buffer on an integrated circuit that minimizes clock skew, (b) checking whether the ideal clock buffer location overlaps a megacell, and (c) finding a location for the clock buffer that is closest to the ideal clock buffer location and that does not overlap a megacell.

Abstract: A capacitor has a titanium nitride layer deposited on a silicon substrate for stress reduction and adherence promotion, and a layer of tantalum is deposited thereon. The tantalum layer is oxidized to produce a tantalum pentoxide layer. A top electrode of metal or polysilicon is then deposited on the tantalum pentoxide layer. The top electrode may be made from polysilicon or a similar semiconducting material so that a space charge layer will form in the electrode which will change the rate at which the capacitor charges and discharges. Alternatively, the top electrode may be made from metal to provide an optimal linear response for use in analog applications. Further, an undoped polysilicon layer may be provided above the tantalum pentoxide layer to store charge for non-volatile memory applications. For this purpose, polysilicon can be used to form the top electrode; alternatively, materials such as silicon nitride may be used.

Abstract: A system and method for managing device configuration changes. The system and method preferably comprises a management station which issues a configuration change request to a management device and waits for a reply from the managed device. The managed device receives the configuration change request from the management station and processes the change request until the configuration change request is durable on the managed device. The managed device then returns a status to the management station indicating that the configuration request is durable. The management station receives the status from the managed device and stops waiting for reply. In the meantime, the managed device continues processing the configuration change request.

Abstract: Data consistency is verified between geographically separated and connected active and mirroring data processing systems by creating metadata which describes user data, such as a cyclical redundancy code (CRC), and time stamp information which describes the time at which user data was first stored on the active system. The metadata and the time stamp information sent from the active system is compared at the mirroring system with the time stamp information and metadata read from the mirroring system. Upon detecting a discrepancy when comparing the metadata from the active and mirroring systems, the user data from the active or mirroring system which is less current temporally, as determined by the time stamp information, is replaced by the user data from the other one of the active or mirroring systems having the more current temporal time stamp information.

Abstract: A system and method for monitoring and managing devices on a network. The system and method preferably comprises a proxy server connected to the network and a managed device connected to the proxy server. The system further comprises storage means for storing a device management application program associated with the managed device, and a management station in communication with the managed device via the proxy server and in communication with the storage means. The management station preferably is configured to retrieve the device management application program from the storage means and process the device management application program. As the management station processes the device management application program, the management station is able to monitor and manage the managed device.