Abstract: A method for measuring electromigration includes the steps of measuring a corresponding voltage increase across an interconnect as a function of time for a plurality of nonzero heating rates and calculating an interconnect integrity from the voltage increase.

Abstract: Disclosed is a method of planarizing an array of plastically-deformable electrical contacts on an integrated circuit. An integrated circuit is placed on a plate with an array of plastically-deformable electrical contacts substantially parallel to and facing the plate, thereby creating an assembly. The integrated circuit is placed above the plate such that the weight of the integrated circuit bears down on the array of plastically-deformable electrical contacts. The assembly is then heated sufficiently to cause individual ones of the plastically-deformable electrical contacts to locally soften but not to cause said individual ones of the electrical contacts to liquefy throughout their volumes. The weight of the integrated circuit applies a force to the softened plastically-deformable electrical contacts, thereby resulting in their planarization.

Abstract: A test signal is propagated through at least a portion of the circuit from a respective input. The test signal is based on a row of a k-wise, &egr;-discrepant matrix. Cells are identified whose outputs have a constant response to the test signal and the inputs of the identified cells are combined with the inputs of the circuit. The process is iteratively repeated until the output of the circuit is reached. The circuit inputs and inputs of identified cells are selected as test points.

Abstract: An apparatus for planarizing a surface of a semiconductor wafer includes a wafer support configured to receive the semiconductor wafer so that the surface of the semiconductor wafer projects from the wafer support. The apparatus also includes a polishing member configured in the form of an endless unitary belt which is devoid of seams. The endless unitary belt is (i) positioned in contact with the surface of the semiconductor wafer and (ii) capable of moving in a linear direction relative to the surface of the semiconductor wafer so as to planarize the surface of the semiconductor wafer. An associated method of linearly planarizing a surface of a semiconductor is also described.

Abstract: A testing system includes a controller, a device driver for the controller, and a processor. The controller is operable to control a device coupled thereto. The device driver is operable to provide a generic interface for data transfers to and from the controller. The processor is coupled to coupled to the controller and is operable to execute a test script having a plurality of script commands. Moreover, the processor is operable to transfer test data to the controller via the generic interface of the device driver in response to executing a first script command of the plurality of script commands. The processor is also operable to receive status information from the controller via the controller generic interface.

Abstract: True paths are identified in a timing graph of a circuit in which the timing graph contains known false paths containing nodes of at least two sets selected from FROM, THROUGH and TO nodes. The false paths are processed to include sets of FROM and TO nodes and then transformed into equivalent sets of two logical false paths. True path intervals are constructed as logical subgraphs that do not describe any equivalent false path. In preferred embodiments, the process is carried out by a computer under control of a computer readable program.

Abstract: A system and method for fax transmission over a fax relay network that includes at least a wideband portion and a narrowband portion, includes a first fax relay gateway communicatively connecting a sending fax machine on the wideband portion of the network to the narrowband portion of the network, the first fax relay gateway receiving image data from the sending fax machine and outputting digitized image data in accordance with a data rate of the narrowband portion of the fax relay network. A second fax relay gateway, communicatively connects a receiving fax machine to the narrowband portion of the network. At least one of the first fax relay gateway or the second fax relay gateway includes a control process that determines whether an amount of data stored in a buffer in the fax relay gateway is greater or less than a particular threshold or determines that the amount of jitter in the narrow band network exceeds a particular threshold, and if so, initiates a retrain procedure to adjust the fax data rate.

Abstract: In this method for hierarchical extraction of interconnect parasitic data for integrated circuits, a representation of coupled interconnects and polygon data copied from an upper level to a lower level is simplified so that the coupled interconnects and the polygon data are considered to be ground wires. This method also features instance-specific management of hardmac data from copied hardmac views to create SPEF files using both chip level and macro level back-annotation in a hierarchical representation.

Abstract: A dual plasma process generates a microwave neutral plasma remote from a semiconductor wafer and a radio frequency (RF) ionized plasma adjacent to the wafer for simultaneous application to the wafer. A first gas flows through a microwave plasma generation area, without a second gas in the gas flow, to generate the neutral microwave plasma. The second gas is added to the gas flow downstream of the microwave plasma generation area prior to an RF plasma generation area.

Abstract: Increased resolution is available from acid-catalyzed photoresist used in fabricating integrated circuits by inhibiting chemically-basic contaminants from contacting the photoresist placed above an IC structure which emits those chemically-basic contaminants. The inhibition can result from physical barrier characteristics of a barrier layer placed between the contaminant-emitting surface and the overlying layer of photoresist, or the layer of barrier material may contain acid moieties which chemically neutralize the emitted chemically-basic contaminants before the contaminants reach the photoresist.

Abstract: A structure for receiving electrical signals near a central portion of the structure and distributing the electrical signals to a peripheral portion of the structure. The structure has a first set of contacts arranged in an array near the central portion of the structure. Electrically conductive traces connect the first set of contacts to a second set of contacts, where each of the electrically conductive traces has at least a first segment, a second segment, and a third segment. The first segment of each of the electrically conductive traces has relatively narrow width and spacing. The first segment of each of the electrically conductive traces is connected on a first end of the first segment to one of the first set of contacts and on a second end of the first segment to the second segment of each of the electrically conductive traces. The second segment of each of the electrically conductive traces has relatively intermediate width and spacing.

Abstract: An integrated circuit device with reduced noise is described. In traditional simultaneous output switching integrated circuits the noise is proportional to the number of concurrently switching outputs. This excessive supply noise can cause the integrated circuit to malfunction through the loss of data. In the present invention, switching supply noise is reduced in the device without increasing the number of input-output pins by synchronously skewing the output driver. In a preferred embodiment, flip-flops are used to control the phase of the switching outputs in order to reduce the noise and instantaneous power by the number of phase assignments.

Abstract: An ADSL central office transmission system for transmitting downstream DMT signals to a plurality of remote ADSL transceiver is disclosed. The system includes a DMT digital signal transceiver that generates a time division multiplexed digital signal that includes a plurality of DMT signals to be sent on a plurality of ADSL lines. A digital to analog converter converts the time division multiplexed digital signal into a time division multiplexed analog signal that includes a plurality of analog DMT signals. The analog to digital converter has an output that outputs the time division multiplexed analog signal. A switch selectively connects the output of the digital to analog converter to each of a plurality of transmitters. The transmitters are configured to drive the plurality of ADSL lines. Thus, the plurality ADSL lines are driven by the plurality of analog DMT signals.

Abstract: According to an embodiment of the invention, a DS-CDMA receiver receives an input signal which comprises a plurality of received signals that are received over a corresponding plurality of antennae. These signals are demodulated and sampled to create digital signals. The digital signals are decorrelated and each of the decorrelated signals are multiplied by a weight to derive weighted estimates. The weighted estimates are summed to generate an estimate of an information symbol. The weights are based upon a cross correlation between the decorrelated signals and a desired signal. According to the invention, this cross correlation may be derived by filtering a pilot signal.

Abstract: Methods and associated apparatus for performing concurrent I/O operations on a common shared subset of disk drives (LUNs) by a plurality of RAID controllers. The methods of the present invention are operable in all of a plurality of RAID controllers to coordinate concurrent access to a shared set of disk drives. The plurality of RAID controllers operable enhance the performance of a RAID subsystem by better utilizing available processing power among the plurality of RAID controllers. Each of a plurality of RAID controllers may actively process different I/O requests on a common shared subset of disk drives. One of the plurality of controllers is designated as primary with respect to a particular shared subset of disk drives. The plurality of RAID controllers then exchange messages over a communication medium to coordinate concurrent access to the shared subset of disk drives through the primary controller.

Abstract: Provided is a technique for circuit delay prediction in which blocks (preferably, non-overlapping blocks) are specified, each of the blocks including a portion of the circuit. Delay calculation collars (DCCs) are then defined for the blocks, the DCCs including complete dependency information required to calculate delay within the blocks. Next, delay is calculated for the blocks based on the DCCs and delay is calculated for the circuit based on the DCCs. The DCCs are then modified as necessary based on results of either or both of the delay calculation for the blocks or the circuit. The delay calculation and DCC modification steps are then repeated.

Abstract: A thermally stable inter-metal dielectric for interlayer dielectric material has enhanced adhesiveness by introduction of an adhesive material. The adhesive material may reside only at the interface of the inter-metal dielectric or interlayer dielectric with adjacent metalization and polysilicon layers. A disclosed thermally stable intermetal dielectric is a fluorinated polymer such as polyfluoropyreline. A disclosed adhesive material is a highly polar material such as a thiofluorocarbon. These materials may be deposited by chemical vapor deposition by first activating fluoropyreline monomer and di(thiodifluoromethane) in a heated activation chamber to convert them to a form suitably reactive to form a polymeric dielectric on a wafer surface.

Abstract: A method for laying out input/output (I/O) pairs, each including an I/O cell and a pad, on an integrated circuit die. Size information is obtained for each of a first I/O pair and a second I/O pair. A minimum pad spacing criterion is obtained which specifies a minimum distance between the pad in the first I/O pair and an element of the second I/O pair, and the first I/O pair and the second I/O pair are laid out so as to satisfy the minimum pad spacing criterion. Also provided is a method for laying out pads for input/output (I/O) cells on an integrated circuit die in which size information is obtained for each of a first I/O cell pad and a second I/O cell pad. A minimum pad spacing criterion is obtained, and the first I/O cell pad and the second I/O cell pad are laid out so as to satisfy the minimum pad spacing criterion.

Abstract: A method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the isolation punchthrough tolerance and the SER immunity of the device. The additional well tub is deposited to a depth that is shallower than the standard well tub. The additional well tub is deposited using an ion implantation process using the same mask set as that used for the threshold voltage adjustment deposition. Thus, no additional mask layer is required to deposit the additional well tub, and the all of the expenses normally associated with an additional mask layer are avoided.

Abstract: A decoder for decoding convolutionally encoded precoding data is described. The precoding sequence consists of two subsequences t and b; the value of t corresponds to a convolutional encoder state at a particular time. The a priori probability Pr(ti) that the subsequence t has a particular value ti is generated. In the preferred embodiment, the metric function that is applied to a test sequence including ti is then biased by adding (&sgr;2/&agr;2) ln(Pr(ti)), where &agr;2 is the signal average energy per symbol of the transmitted data, &sgr;2 is the variance of the noise added by a channel through which the data is transmitted. The resulting metric is then used by an MLSE decoder such as a Viterbi decoder to decode the received data.