Abstract: A delay-locked loop circuit is provided which includes a delay-locked loop, a delay element and a multiplexer. The delay-locked loop has a reference clock input, a feedback clock input and a clock output. The delay element has a delay input which is coupled to the clock output and a delay output. The multiplexer has a first multiplexer input which is coupled to the clock output, a second multiplexer input which is coupled to the delay output and a multiplexer output which is coupled to the feedback input.

Abstract: The present invention describes a system and method for encoding a sequence of 64 bit digital data words into a sequence of 65 bit codewords having constraints of (d=0, G=11/I=10) for recording upon a magnetic medium within a magnetic recording channel are disclosed. The method for encoding a sequence of 64 bit digital data words into a sequence of codewords having 65 bits, comprising the steps of dividing each 64-bit digital data word into 8-bit bytes, encoding two 8-bit bytes to form a 17-bit word, forming five 11-bit intermediate blocks from the 8-bit bytes, encoding the five 11-bit intermediate blocks, and concatenating the five encoded 11-bit intermediate blocks and uncoded and unconstrained bits from the 64 bit digital data word to form a 65 bit codeword. A corresponding decoding method is also described. A byte shuffler may be used in the processing.

Abstract: A method of insuring continuous processing of messages from a Work FIFO in a message passing interface between a requesting module and a receiving module. Each module has access to two queues in the message passing interface, and each queue has a Work FIFO for containing message frames to be processed and a Free FIFO for containing empty message frames. The method includes a step of monitoring the number of free messages in the Free FIFO of the receiving module. When that number falls below a selectable early warning level, the receiving module is alerted. The receiving module then sends an early warning level signal to the requesting module, and additional free messages are posted to the Free FIFO of the receiving module. This posting of additional free messages allows the continued processing, by the receiving module, of messages from the receiving module work FIFO.

Abstract: A method is disclosed for applying underfill to a flip-chip package comprising integrated circuit die and a substrate. First, a first non-filled no flow flux-underfill is applied to a plurality of solder bumps disposed on an active surface of the integrated circuit die. Next, the integrated circuit die is placed on the substrate such that the solder bumps align with corresponding bond pads on the substrate, thereby creating an assembly. A second filler-loaded no flow flux-underfill is then dispensed on a side of the substrate such that the second filler-loaded no flow flux-underfill flows by capillary action between the die and substrate to fill a gap therebetween. Finally, the assembly is passed through a furnace such that both the first non-filled no flow flux-underfill and the second filled no flow flux-underfill are cured, and such that the solder bumps are reflowed.

Abstract: A method for concentric metal density power distribution is disclosed that reduces metal density and increases available area for routing clock and signal traces. A method of concentric metal density power distribution includes the steps of partitioning an area of standard cells in an integrated circuit chip into a plurality of power regions, forming a power boundary around each of the plurality of power regions, and forming a plurality of concentric straps in a metal layer of the integrated circuit chip wherein each of the plurality of concentric straps has a strap width that varies from a maximum strap width at a periphery of each of the plurality of power regions to a minimum strap width toward a center of each of the plurality of power regions.

Abstract: A method for testing a series of functional blocks within an integrated circuit. Each of the functional blocks in the series is tested to determine a minimum parameter value and a maximum parameter value associated with each of the functional blocks. A minimum parameter delta value is calculated for each of the functional blocks in the series. The minimum parameter delta value is the minimum parameter value associated with a given one of the functional blocks subtracted from the minimum parameter value for a functional block immediately following the given one of the functional blocks in the series. A maximum parameter delta value is also calculated for each of the functional blocks in the series. The maximum parameter delta value is the maximum parameter value associated with the given one of the functional blocks subtracted from the maximum parameter value for the functional block immediately following the given one of the functional blocks in the series.

Abstract: A memory controller for controlling a multiple bank DRAM comprises a pool/queue state machine, a plurality of transaction processor state machines, a command arbitor and a plurality of bank state machines, preferably one bank state machine for each bank in the DRAM. As transactions are received by the controller, they are allocated by the pool/queue state machine to one of the transaction processor state machines. The receiving transaction processor state machine first checks if the memory bank corresponding to the read/write address is available. Once the bank is available, the transaction processor state machine then sends RAS and CAS requests request to the arbitor. The arbitor receives this request and arbitrates between it and other pending requests (both CAS and RAS requests from the other transaction processor state machines and precharge requests from the bank state machines).

Abstract: A system and method for arbitrating bandwidth between nodes on a network. A count, referred to as the idle gap count, stores the number of nodes that require bandwidth on the network. The count is passed between the nodes and bandwidth is allocated accordingly to effectuate optimization and fair allocation of bandwidth on the network.

Abstract: A processor including in-circuit emulation means comprising a plurality of scan chains of serially connected registers coupled to a means for enabling a serial scan procedure to be carried out, a first scan chain including an address register for providing an address on an address bus to memory, and means for incrementing the value in the address register under control of the processor, the scan chains being arranged to control the processor for incrementing the address register, and the scan chains including a data register coupled to the data bus of the memory to read/write data.

Abstract: A method for forming an alignment feature on a substrate. The alignment feature is of the type concurrently formed with an electrically conductive layer overlying an electrically nonconductive layer having vias. The vias are filled with an electrically conductive material, and the alignment feature has a smaller aspect ratio than the vias. The alignment feature is not filled with the electrically conductive material when a first amount of the electrically conductive material, sufficient to just fill the vias, is deposited on the substrate. The first amount of the electrically conductive material within the alignment feature is not sufficient to prevent the alignment feature in the electrically conductive layer from distorting, and thereby reducing the effectiveness of the alignment feature. The improvement is in depositing an additional amount of the electrically conductive material on the substrate.

Abstract: An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0.25 &mgr;m SRAM design having one or more N wells of a conventional depth not exceeding about 0.5 &mgr;m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 &mgr;m. The deep N well of the 0.25 &mgr;m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 &mgr;m, and preferably at least about 2 &mgr;m.

Abstract: A method and system for displaying a series of video frames in reverse order. The video frames are received in groups of pictures (GOPs) from a storage medium. The method comprises steps of (a) decoding and storing a number of frames from an initial GOP into frame buffers according to an ordering of the frame buffers, (b) displaying the stored frames according to the reverse ordering of the frame buffers, (c) decoding and storing a number of frames from a first preceding GOP according to the reverse ordering of the frame buffers, (d) displaying the stored frames according to the ordering of the frame buffers, (e) decoding and storing a number of frames from a second preceding GOP according to the ordering of the frame buffers, and (f) repeating steps (b)-(e),for prior first and second preceding GOPs.

Abstract: The present invention is directed to laying out connection points and routing a signal from an input terminal to the connection points for use in signal distribution to control skew. A pattern of diamond-shaped rings is constructed, each of the diamond-shaped rings including an inner diamond, an outer diamond and all space between the inner diamond and the outer diamond, where the diamond-shaped rings are arranged such that each point within a specified area is included within at least one diamond-shaped ring. A center point is identified for each of the diamond-shaped rings and each center point is designated as a connection point. A connection is then routed between the input terminal and each of plural of the connection points. The invention also is directed to routing a signal from one of plural connection points to a pin so as to control skew.

Abstract: A method of forming an electrically conductive interconnect on a substrate. An interconnection feature is formed on the substrate, and a first barrier layer is deposited on the substrate. The first barrier layer consists essentially of a diamond film. A seed layer consisting essentially of copper is deposited on the substrate, and a conductive layer consisting essentially of copper is deposited on the substrate. Thus, by using a diamond film as the barrier layer, diffusion of the copper from the conductive layer into the material of the substrate is substantially reduced and preferably eliminated.

Abstract: A flipchip packaged integrated circuit comprising a substrate, a die and a heatspreader. The die may be configured to electrically attach to the substrate. The heat spreader may be rigidly attached to the die. The die and the heatspreader may have a combined coefficient of thermal expansion when attached. The heatspreader may be configured to match the combined coefficient of thermal expansion and a coefficient of thermal expansion of the substrate.

Abstract: A method for resynthesizing a design of an integrated circuit using a parallel processing mode. A single processing mode is entered by activating a main thread and locking a semaphore associated with the main thread. The design of the integrated circuit is resynthesized using the main thread. Tasks to be accomplished in the parallel processing mode are identified. The semaphore associated with the main thread is unlocked, and the operation of the single processing mode is ceased. Ordinal threads are activated by unlocking a semaphore associated with each ordinal thread. The tasks are processed in parallel by assigning the tasks to the ordinal threads and the main thread. Upon completion of one of the assigned tasks by one of the ordinal threads, it is determined whether an additional task remains to be assigned. In the case where the additional task remains, the additional task is assigned to the completed one of the ordinal threads.

Abstract: A system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry. The user can view full or partial simulation and design results simultaneously, on a single display window. The synthesis process uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is generally a series of transformations operating upon various levels of design representations. At each level, the design can be simulated and reviewed in schematic diagram form. The simulation results can be displayed immediately adjacent to signal lines on the diagram to which they correspond. In one embodiment, design rule violations are processed by an expert system to suggest possible corrections or alterations to the design which will eliminate the design rule violations.

Abstract: A method for defining electrical components enables a layout tool to include functionally extraneous cells in an integrated circuit design without significant adverse impact to the operation of the logically functional cells. The method defines the description of a first functionally extraneous cell for a layout tool so an initial layout of the die produced by the layout tool does not functionally couple the first functionally extraneous cell to a second functionally extraneous cell. The description of the functionally extraneous cell is altered so that the layout tool produces a second layout of the die that functionally couples the first and second functionally extraneous cells without altering the position of the second functionally extraneous cell with respect to a logically functional cell. The description of the functionally extraneous cell complies with the description constraints for cells.

Abstract: Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer.

Abstract: Methods and associated structure for enabling immediate availability of a disk array storage device. In particular, the methods and associated structure of the present invention permit access to a logical unit of a storage system immediately following creation of the logical unit. Initialization of the logical unit to initialize redundancy information therein proceeds in parallel with host system access to the storage space of the logical unit. The initialization process maintains a boundary parameter value indicative of the progress of the initialization process. Storage space above the boundary has had its redundancy information initialized while storage space below the boundary has not. Where an I/O request is entirely above the boundary, it is processed normally in accordance with the management of the logical unit. Where part of an I/O request is below the boundary, it is processed in a special manner that assures integrity of the redundancy data.